[mlir][spirv] Add OpExtension "SPV_INTEL_bfloat16_conversion"

[mshahneo]

Summary

Add Intel-specific "SPV_INTEL_bfloat16_conversion" extension and
capability (Bfloat16ConversionINTEL), and
two ops (OpConvertFToBF16INTEL, OpConvertBF16ToFINTEL)
that are introduced by this extension.
These ops allow BF16 to Float conversion and vice-versa.

Reference Specification:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_bfloat16_conversion.asciidoc

[antiagainst]

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td

41

This does not match with the assembly format?

48

The example does not match the assembly format in the following?

101

Same here. Need to update to match the assembly format.

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

2213

Could you add negative tests triggering this in test/Dialect/SPIRV/IR?

[mshahneo]

Add Negative test cases
Fix assembly format mismatch with the documentation example

Depends on D147087

[mshahneo]

Thank you so much for pointing out the issues.
Addressed them :).

[mshahneo]

Hi @antiagainst ,

Could you please help me commit the change, I do not have commit access.
Thank you so much in advance :).

Best Regards,
Abdullah

[antiagainst]

In D147087#4237545, @mshahneo wrote:

Hi @antiagainst ,

Could you please help me commit the change, I do not have commit access.
Thank you so much in advance :).

Best Regards,
Abdullah

Sure thing! Done.

[mshahneo]

Thank you so much :)

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

 def SPV_INTEL_fpga_reg                           : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 4023>;
 def SPV_INTEL_long_constant_composite            : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 4024>;
 def SPV_INTEL_optnone                            : I32EnumAttrCase<"SPV_INTEL_optnone", 4025>;
 def SPV_INTEL_debug_module                       : I32EnumAttrCase<"SPV_INTEL_debug_module", 4026>;
 def SPV_INTEL_fp_fast_math_mode                  : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 4027>;
 def SPV_INTEL_memory_access_aliasing             : I32EnumAttrCase<"SPV_INTEL_memory_access_aliasing", 4028>;
 def SPV_INTEL_split_barrier                      : I32EnumAttrCase<"SPV_INTEL_split_barrier", 4029>;
 def SPV_INTEL_joint_matrix                       : I32EnumAttrCase<"SPV_INTEL_joint_matrix", 4030>;
+def SPV_INTEL_bfloat16_conversion                : I32EnumAttrCase<"SPV_INTEL_bfloat16_conversion", 4031>;
 
 def SPV_NV_compute_shader_derivatives    : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 5000>;
 def SPV_NV_cooperative_matrix            : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 5001>;
 def SPV_NV_fragment_shader_barycentric   : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 5002>;
 def SPV_NV_geometry_shader_passthrough   : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 5003>;
 def SPV_NV_mesh_shader                   : I32EnumAttrCase<"SPV_NV_mesh_shader", 5004>;
 def SPV_NV_ray_tracing                   : I32EnumAttrCase<"SPV_NV_ray_tracing", 5005>;
 def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 5006>;
SPIRV_I32EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
       SPV_INTEL_arbitrary_precision_integers, SPV_INTEL_arbitrary_precision_floating_point,
       SPV_INTEL_kernel_attributes, SPV_INTEL_fpga_memory_accesses,
       SPV_INTEL_fpga_cluster_attributes, SPV_INTEL_loop_fuse,
       SPV_INTEL_fpga_buffer_location, SPV_INTEL_arbitrary_precision_fixed_point,
       SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_INTEL_blocking_pipes,
       SPV_INTEL_fpga_reg, SPV_INTEL_long_constant_composite, SPV_INTEL_optnone,
       SPV_INTEL_debug_module, SPV_INTEL_fp_fast_math_mode,
       SPV_INTEL_memory_access_aliasing, SPV_INTEL_split_barrier, SPV_INTEL_joint_matrix,
-      SPV_NV_compute_shader_derivatives, SPV_NV_cooperative_matrix,
+      SPV_INTEL_bfloat16_conversion, SPV_NV_compute_shader_derivatives, SPV_NV_cooperative_matrix,
       SPV_NV_fragment_shader_barycentric, SPV_NV_geometry_shader_passthrough,
       SPV_NV_mesh_shader, SPV_NV_ray_tracing, SPV_NV_sample_mask_override_coverage,
       SPV_NV_shader_image_footprint, SPV_NV_shader_sm_builtins,
       SPV_NV_shader_subgroup_partitioned, SPV_NV_shading_rate,
       SPV_NV_stereo_view_rendering, SPV_NV_viewport_array2, SPV_NV_bindless_texture,
       SPV_NV_ray_tracing_motion_blur, SPV_NVX_multiview_per_view_attributes
     ]>;
 

 }
 
 def SPIRV_C_JointMatrixINTEL                         : I32EnumAttrCase<"JointMatrixINTEL", 6118> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_joint_matrix]>
   ];
 }
 
+def SPIRV_C_Bfloat16ConversionINTEL                         : I32EnumAttrCase<"Bfloat16ConversionINTEL", 6115> {
+  list<Availability> availability = [
+    Extension<[SPV_INTEL_bfloat16_conversion]>
+  ];
+}
+
 def SPIRV_CapabilityAttr :
     SPIRV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [
       SPIRV_C_Matrix, SPIRV_C_Addresses, SPIRV_C_Linkage, SPIRV_C_Kernel, SPIRV_C_Float16,
       SPIRV_C_Float64, SPIRV_C_Int64, SPIRV_C_Groups, SPIRV_C_Int16, SPIRV_C_Int8,
       SPIRV_C_Sampled1D, SPIRV_C_SampledBuffer, SPIRV_C_GroupNonUniform, SPIRV_C_ShaderLayer,
       SPIRV_C_ShaderViewportIndex, SPIRV_C_UniformDecoration, SPIRV_C_SubgroupBallotKHR,
       SPIRV_C_SubgroupVoteKHR, SPIRV_C_StorageBuffer16BitAccess,
       SPIRV_C_StoragePushConstant16, SPIRV_C_StorageInputOutput16, SPIRV_C_DeviceGroup,
SPIRV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [
       SPIRV_C_UniformBufferArrayNonUniformIndexing,
       SPIRV_C_SampledImageArrayNonUniformIndexing,
       SPIRV_C_StorageBufferArrayNonUniformIndexing,
       SPIRV_C_StorageImageArrayNonUniformIndexing,
       SPIRV_C_InputAttachmentArrayNonUniformIndexing,
       SPIRV_C_UniformTexelBufferArrayNonUniformIndexing,
       SPIRV_C_StorageTexelBufferArrayNonUniformIndexing,
       SPIRV_C_ShaderViewportIndexLayerEXT, SPIRV_C_ShaderViewportMaskNV,
-      SPIRV_C_ShaderStereoViewNV, SPIRV_C_JointMatrixINTEL
+      SPIRV_C_ShaderStereoViewNV, SPIRV_C_JointMatrixINTEL, SPIRV_C_Bfloat16ConversionINTEL
     ]>;
 
 def SPIRV_AM_Logical                 : I32EnumAttrCase<"Logical", 0>;
 def SPIRV_AM_Physical32              : I32EnumAttrCase<"Physical32", 1> {
   list<Availability> availability = [
     Capability<[SPIRV_C_Addresses]>
   ];
 }

 
 
 // See https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_types
 // for the definition of the following types and type categories.
 
 def SPIRV_Void : TypeAlias<NoneType, "void">;
 def SPIRV_Bool : TypeAlias<I1, "bool">;
 def SPIRV_Integer : AnyIntOfWidths<[8, 16, 32, 64]>;
+def SPIRV_Int16 : TypeAlias<I16, "Int16">;
 def SPIRV_Int32 : TypeAlias<I32, "Int32">;
 def SPIRV_Float32 : TypeAlias<F32, "Float32">;
 def SPIRV_Float : FloatOfWidths<[16, 32, 64]>;
 def SPIRV_Float16or32 : FloatOfWidths<[16, 32]>;
 def SPIRV_Vector : VectorOfLengthAndType<[2, 3, 4, 8, 16],
                                        [SPIRV_Bool, SPIRV_Integer, SPIRV_Float]>;
 // Component type check is done in the type parser for the following SPIR-V
 // dialect-specific types so we use "Any" here.

 def SPIRV_OC_OpGroupFMulKHR               : I32EnumAttrCase<"OpGroupFMulKHR", 6402>;
 
 def SPIRV_OC_OpTypeJointMatrixINTEL       : I32EnumAttrCase<"OpTypeJointMatrixINTEL", 6119>;
 def SPIRV_OC_OpJointMatrixLoadINTEL       : I32EnumAttrCase<"OpJointMatrixLoadINTEL", 6120>;
 def SPIRV_OC_OpJointMatrixStoreINTEL      : I32EnumAttrCase<"OpJointMatrixStoreINTEL", 6121>;
 def SPIRV_OC_OpJointMatrixMadINTEL        : I32EnumAttrCase<"OpJointMatrixMadINTEL", 6122>;
 def SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL : I32EnumAttrCase<"OpJointMatrixWorkItemLengthINTEL", 6410>;
 
+def SPIRV_OC_OpConvertFToBF16INTEL        : I32EnumAttrCase<"OpConvertFToBF16INTEL", 6116>;
+def SPIRV_OC_OpConvertBF16ToFINTEL        : I32EnumAttrCase<"OpConvertBF16ToFINTEL", 6117>;
+
 def SPIRV_OpcodeAttr :
     SPIRV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
       SPIRV_OC_OpNop, SPIRV_OC_OpUndef, SPIRV_OC_OpSourceContinued,
       SPIRV_OC_OpSource, SPIRV_OC_OpSourceExtension, SPIRV_OC_OpName,
       SPIRV_OC_OpMemberName, SPIRV_OC_OpString, SPIRV_OC_OpLine,
       SPIRV_OC_OpExtension, SPIRV_OC_OpExtInstImport, SPIRV_OC_OpExtInst,
       SPIRV_OC_OpMemoryModel, SPIRV_OC_OpEntryPoint, SPIRV_OC_OpExecutionMode,
       SPIRV_OC_OpCapability, SPIRV_OC_OpTypeVoid, SPIRV_OC_OpTypeBool,
SPIRV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
       SPIRV_OC_OpCooperativeMatrixLoadNV, SPIRV_OC_OpCooperativeMatrixStoreNV,
       SPIRV_OC_OpCooperativeMatrixMulAddNV, SPIRV_OC_OpCooperativeMatrixLengthNV,
       SPIRV_OC_OpSubgroupBlockReadINTEL, SPIRV_OC_OpSubgroupBlockWriteINTEL,
       SPIRV_OC_OpAssumeTrueKHR, SPIRV_OC_OpAtomicFAddEXT, SPIRV_OC_OpGroupIMulKHR,
       SPIRV_OC_OpGroupFMulKHR,
 
       SPIRV_OC_OpTypeJointMatrixINTEL, SPIRV_OC_OpJointMatrixLoadINTEL,
       SPIRV_OC_OpJointMatrixStoreINTEL, SPIRV_OC_OpJointMatrixMadINTEL,
-      SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL
+      SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL,
+
+      SPIRV_OC_OpConvertFToBF16INTEL, SPIRV_OC_OpConvertBF16ToFINTEL
     ]>;
 
 // End opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 
 //===----------------------------------------------------------------------===//
 // SPIR-V op definitions
 //===----------------------------------------------------------------------===//
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td

+//===- SPIRVIntelExtOps.td - Intel SPIR-V extensions ---------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This is the op definition spec of Intel-specific SPIR-V extensions
+// These extensions are not part of Khronos specification but publicly available
+// at (https://github.com/intel/llvm)
+// Supported extensions
+// * SPV_INTEL_bfloat16_conversion
+//===----------------------------------------------------------------------===//
+
+
+#ifndef MLIR_DIALECT_SPIRV_IR_INTEL_EXT_OPS
+#define MLIR_DIALECT_SPIRV_IR_INTEL_EXT_OPS
+
+// -----
+
+def SPIRV_INTELConvertFToBF16Op : SPIRV_IntelVendorOp<"ConvertFToBF16", []> {
+  let summary = "See extension SPV_INTEL_bfloat16_conversion";
+
+  let description = [{
+    Convert value numerically from 32-bit floating point to bfloat16,
+    which is represented as a 16-bit unsigned integer.
+
+    Result Type must be a scalar or vector of integer type.
+    The component width must be 16 bits. Bit pattern in the Result represents a bfloat16 value.
+
+    Float Value must be a scalar or vector of floating-point type.
+    It must have the same number of components as Result Type. The component width must be 32 bits.
+
+    Results are computed per component.
+
+    ```
+    convert-f-to-bf16-op ::= ssa-id `=` `spirv.INTEL.ConvertFToBF16` ssa-use
+                          `:` operand-type `to` result-type
+    ```
+
+    #### Example:
+
+    ```mlir
+    %1 = spirv.ConvertFToBF16 %0 : f32 to i16
+    %3 = spirv.ConvertFToBF16 %2 : vector<3xf32> to vector<3xi16>
+    ```
+
+  }];
+
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPV_INTEL_bfloat16_conversion]>,
+    Capability<[SPIRV_C_Bfloat16ConversionINTEL]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScalarOrVectorOf<SPIRV_Float32>:$operand
+  );
+
+  let results = (outs
+    SPIRV_ScalarOrVectorOf<SPIRV_Int16>:$result
+  );
+  let assemblyFormat = [{
+    $operand attr-dict `:` type($operand) `to` type($result)
+  }];
+
+  let hasVerifier = 1;
+}
+
+// -----
+
+def SPIRV_INTELConvertBF16ToFOp : SPIRV_IntelVendorOp<"ConvertBF16ToF", []> {
+  let summary = "See extension SPV_INTEL_bfloat16_conversion";
+
+  let description = [{
+    Interpret a 16-bit integer as bfloat16 and convert the value numerically to 32-bit floating point type.
+
+    Result Type must be a scalar or vector of floating-point. The component width must be 32 bits.
+
+    Bfloat16 Value must be a scalar or vector of integer type, which is interpreted as a bfloat16 type.
+    The type must have the same number of components as the Result Type. The component width must be 16 bits.
+
+    Results are computed per component.
+
+    ```
+    convert-bf16-to-f-op ::= ssa-id `=` `spirv.INTEL.ConvertBF16ToF` ssa-use
+                          `:` operand-type `to` result-type
+    ```
+
+    #### Example:
+
+    ```mlir
+    %1 = spirv.ConvertBF16ToF %0 : i16 to f32
+    %3 = spirv.ConvertBF16ToF %2 : vector<3xi16> to vector<3xf32>
+    ```
+
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPV_INTEL_bfloat16_conversion]>,
+    Capability<[SPIRV_C_Bfloat16ConversionINTEL]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScalarOrVectorOf<SPIRV_Int16>:$operand
+  );
+
+  let results = (outs
+    SPIRV_ScalarOrVectorOf<SPIRV_Float32>:$result
+  );
+
+  let assemblyFormat = [{
+    $operand attr-dict `:` type($operand) `to` type($result)
+  }];
+  let hasVerifier = 1;
+}
+
+
+// -----
+
+#endif // MLIR_DIALECT_SPIRV_IR_INTEL_EXT_OPS
 No newline at end of file

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td

 include "mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVBitOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVCastOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVJointMatrixOps.td"
+include "mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVGLOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVImageOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVIntegerDotProductOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVCLOps.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 #endif // MLIR_DIALECT_SPIRV_IR_OPS

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

 //===----------------------------------------------------------------------===//
 
 LogicalResult spirv::ConvertUToFOp::verify() {
   return verifyCastOp(*this, /*requireSameBitWidth=*/false,
                       /*skipBitWidthCheck=*/true);
 }
 
 //===----------------------------------------------------------------------===//
+// spirv.INTELConvertBF16ToFOp
+//===----------------------------------------------------------------------===//
+
+LogicalResult spirv::INTELConvertBF16ToFOp::verify() {
+  auto operandType = getOperand().getType();
+  auto resultType = getResult().getType();
+  // ODS checks that vector result type and vector operand type have the same
+  // shape.
+  if (auto vectorType = operandType.dyn_cast<VectorType>()) {
+    unsigned operandNumElements = vectorType.getNumElements();
+    unsigned resultNumElements = resultType.cast<VectorType>().getNumElements();
+    if (operandNumElements != resultNumElements) {
+      return emitOpError(
+          "operand and result must have same number of elements");
+    }
+  }
+  return success();
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.INTELConvertFToBF16Op
+//===----------------------------------------------------------------------===//
+
+LogicalResult spirv::INTELConvertFToBF16Op::verify() {
+  auto operandType = getOperand().getType();
+  auto resultType = getResult().getType();
+  // ODS checks that vector result type and vector operand type have the same
+  // shape.
+  if (auto vectorType = operandType.dyn_cast<VectorType>()) {
+    unsigned operandNumElements = vectorType.getNumElements();
+    unsigned resultNumElements = resultType.cast<VectorType>().getNumElements();
+    if (operandNumElements != resultNumElements) {
+      return emitOpError(
+          "operand and result must have same number of elements");
+    }
+  }
+  return success();
+}
+
+//===----------------------------------------------------------------------===//
 // spirv.EntryPoint
 //===----------------------------------------------------------------------===//
 
 void spirv::EntryPointOp::build(OpBuilder &builder, OperationState &state,
                                 spirv::ExecutionModel executionModel,
                                 spirv::FuncOp function,
                                 ArrayRef<Attribute> interfaceVars) {
   build(builder, state,

mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir

+// RUN: mlir-opt -split-input-file -verify-diagnostics %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// spirv.INTEL.ConvertFToBF16
+//===----------------------------------------------------------------------===//
+
+spirv.func @f32_to_bf16(%arg0 : f32) "None" {
+  // CHECK: {{%.*}} = spirv.INTEL.ConvertFToBF16 {{%.*}} : f32 to i16
+  %0 = spirv.INTEL.ConvertFToBF16 %arg0 : f32 to i16
+  spirv.Return
+}
+
+// -----
+
+spirv.func @f32_to_bf16_vec(%arg0 : vector<2xf32>) "None" {
+  // CHECK: {{%.*}} = spirv.INTEL.ConvertFToBF16 {{%.*}} : vector<2xf32> to vector<2xi16>
+  %0 = spirv.INTEL.ConvertFToBF16 %arg0 : vector<2xf32> to vector<2xi16>
+  spirv.Return
+}
+
+// -----
+
+spirv.func @f32_to_bf16_unsupported(%arg0 : f64) "None" {
+  // expected-error @+1 {{operand #0 must be Float32 or vector of Float32 values of length 2/3/4/8/16, but got}}
+  %0 = spirv.INTEL.ConvertFToBF16 %arg0 : f64 to i16
+  spirv.Return
+}
+
+// -----
+
+spirv.func @f32_to_bf16_vec_unsupported(%arg0 : vector<2xf32>) "None" {
+  // expected-error @+1 {{operand and result must have same number of elements}}
+  %0 = spirv.INTEL.ConvertFToBF16 %arg0 : vector<2xf32> to vector<4xi16>
+  spirv.Return
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// spirv.INTEL.ConvertBF16ToF
+//===----------------------------------------------------------------------===//
+
+spirv.func @bf16_to_f32(%arg0 : i16) "None" {
+  // CHECK: {{%.*}} = spirv.INTEL.ConvertBF16ToF {{%.*}} : i16 to f32
+  %0 = spirv.INTEL.ConvertBF16ToF %arg0 : i16 to f32
+  spirv.Return
+}
+
+// -----
+
+spirv.func @bf16_to_f32_vec(%arg0 : vector<2xi16>) "None" {
+    // CHECK: {{%.*}} = spirv.INTEL.ConvertBF16ToF {{%.*}} : vector<2xi16> to vector<2xf32>
+    %0 = spirv.INTEL.ConvertBF16ToF %arg0 : vector<2xi16> to vector<2xf32>
+    spirv.Return
+}
+
+// -----
+
+spirv.func @bf16_to_f32_unsupported(%arg0 : i16) "None" {
+  // expected-error @+1 {{result #0 must be Float32 or vector of Float32 values of length 2/3/4/8/16, but got}}
+  %0 = spirv.INTEL.ConvertBF16ToF %arg0 : i16 to f16
+  spirv.Return
+}
+
+// -----
+
+spirv.func @bf16_to_f32_vec_unsupported(%arg0 : vector<2xi16>) "None" {
+  // expected-error @+1 {{operand and result must have same number of elements}}
+  %0 = spirv.INTEL.ConvertBF16ToF %arg0 : vector<2xi16> to vector<3xf32>
+  spirv.Return
+}

mlir/test/Target/SPIRV/intel-ext-ops.mlir

+// RUN: mlir-translate -no-implicit-module -test-spirv-roundtrip -split-input-file %s | FileCheck %s
+
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Bfloat16ConversionINTEL], [SPV_INTEL_bfloat16_conversion]> {
+  // CHECK-LABEL: @f32_to_bf16
+  spirv.func @f32_to_bf16(%arg0 : f32) "None" {
+    // CHECK: {{%.*}} = spirv.INTEL.ConvertFToBF16 {{%.*}} : f32 to i16
+    %0 = spirv.INTEL.ConvertFToBF16 %arg0 : f32 to i16
+    spirv.Return
+  }
+
+  // CHECK-LABEL: @f32_to_bf16_vec
+  spirv.func @f32_to_bf16_vec(%arg0 : vector<2xf32>) "None" {
+    // CHECK: {{%.*}} = spirv.INTEL.ConvertFToBF16 {{%.*}} : vector<2xf32> to vector<2xi16>
+    %0 = spirv.INTEL.ConvertFToBF16 %arg0 : vector<2xf32> to vector<2xi16>
+    spirv.Return
+  }
+
+  // CHECK-LABEL: @bf16_to_f32
+  spirv.func @bf16_to_f32(%arg0 : i16) "None" {
+    // CHECK: {{%.*}} = spirv.INTEL.ConvertBF16ToF {{%.*}} : i16 to f32
+    %0 = spirv.INTEL.ConvertBF16ToF %arg0 : i16 to f32
+    spirv.Return
+  }
+
+  // CHECK-LABEL: @bf16_to_f32_vec
+  spirv.func @bf16_to_f32_vec(%arg0 : vector<2xi16>) "None" {
+    // CHECK: {{%.*}} = spirv.INTEL.ConvertBF16ToF {{%.*}} : vector<2xi16> to vector<2xf32>
+    %0 = spirv.INTEL.ConvertBF16ToF %arg0 : vector<2xi16> to vector<2xf32>
+    spirv.Return
+  }
+}