[AArch64] Add v8.9a/v9.4a FEAT_ATS1A

[lenary]

Summary

FEAT_ATS1A adds three new AT system instruction aliases. This feature is
optional from v8.9a/v9.4a. FEAT_ATS1A is a very late addition to the
2022 A-profile VMSA extension, and has not yet been added to the public
docs available on developer.arm.com

These AT instructions are added without a command-line flag or feature,
because it is system-instruction only, and FEAT_S1PIE also has no
command-line flag.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;
 def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;
 
 let Requires = [{ {AArch64::FeaturePAN_RWV} }] in {
 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
 }
 
+// v8.9a/v9.4a FEAT_ATS1A
+def : AT<"S1E1A", 0b000, 0b0111, 0b1001, 0b010>;
+def : AT<"S1E2A", 0b100, 0b0111, 0b1001, 0b010>;
+def : AT<"S1E3A", 0b110, 0b0111, 0b1001, 0b010>;
+
 //===----------------------------------------------------------------------===//
 // DMB/DSB (data barrier) instruction options.
 //===----------------------------------------------------------------------===//
 
 class DB<string name, bits<4> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 

llvm/test/MC/AArch64/armv8.9a-ats1a.s

+// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s
+
+at s1e1a, x1
+// CHECK: at s1e1a, x1                        // encoding: [0x41,0x79,0x08,0xd5]
+
+at s1e2a, x1
+// CHECK: at s1e2a, x1                        // encoding: [0x41,0x79,0x0c,0xd5]
+
+at s1e3a, x1
+// CHECK: at s1e3a, x1                        // encoding: [0x41,0x79,0x0e,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt

+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s
+
+[0x41,0x79,0x08,0xd5]
+# CHECK: at s1e1a, x1
+
+[0x41,0x79,0x0c,0xd5]
+# CHECK: at s1e2a, x1
+
+[0x41,0x79,0x0e,0xd5]
+# CHECK: at s1e3a, x1