[clang-format] Don't squash Verilog escaped identifiers

[sstwcw]

Summary

An escaped identifier always needs a space following it so the parser
can tell it apart from the next token.

The unit tests are changed to use FormatTestBase.h because we need the
2-argument version of verifyFormat. We also added the messUp
virtual function because Verilog needs a different version of it.

[MyDeveloperDay]

clang/unittests/Format/FormatTestVerilog.cpp

897

is this correct? do you have an anonymous namespace?

[sstwcw]

clang/unittests/Format/FormatTestVerilog.cpp

897

It is correct. The class FormatTestVerilog is only used in this file. Other files have it too. I didn't notice it when I copied the first few lines from FormatTest.cpp this time, but I probably forgot to add it when creating the file.

[HazardyKnusperkeks]

clang/unittests/Format/FormatTestVerilog.cpp

19

Drop that virtual.

clang/lib/Format/TokenAnnotator.cpp

if (Style.isCpp()) {
     if ((Left.isOneOf(tok::kw_static, tok::kw_public, tok::kw_private,
                       tok::kw_protected) ||
          Left.isOneOf(Keywords.kw_final, Keywords.kw_abstract,
                       Keywords.kw_native)) &&
         Right.is(TT_TemplateOpener)) {
       return true;
     }
   } else if (Style.isVerilog()) {
+    // An escaped identifier ends with whitespace.
+    if (Style.isVerilog() && Left.is(tok::identifier) &&
+        Left.TokenText[0] == '\\') {
+      return true;
+    }
     // Add space between things in a primitive's state table unless in a
     // transition like `(0?)`.
     if ((Left.is(TT_VerilogTableItem) &&
          !Right.isOneOf(tok::r_paren, tok::semi)) ||
         (Right.is(TT_VerilogTableItem) && Left.isNot(tok::l_paren))) {
       const FormatToken *Next = Right.getNextNonComment();
       return !(Next && Next->is(tok::r_paren));
     }

clang/unittests/Format/FormatTestBase.h

 #define DEBUG_TYPE "format-test-base"
 
 class FormatTestBase : public ::testing::Test {
 protected:
   enum StatusCheck { SC_ExpectComplete, SC_ExpectIncomplete, SC_DoNotCheck };
 
   virtual FormatStyle getDefaultStyle() const { return getLLVMStyle(); }
 
+  virtual std::string messUp(llvm::StringRef Code) const {
+    return test::messUp(Code);
+  }
+
   std::string format(llvm::StringRef Code,
                      const std::optional<FormatStyle> &Style = {},
                      StatusCheck CheckComplete = SC_ExpectComplete,
                      const std::vector<tooling::Range> &Ranges = {}) {
     LLVM_DEBUG(llvm::errs() << "---\n");
     LLVM_DEBUG(llvm::errs() << Code << "\n\n");
     auto NonEmptyRanges =
         !Ranges.empty()
protected:
   void _verifyFormat(const char *File, int Line, llvm::StringRef Code,
                      const std::optional<FormatStyle> &Style = {}) {
     _verifyFormat(File, Line, Code, test::messUp(Code), Style);
   }
 
   void _verifyIncompleteFormat(const char *File, int Line, llvm::StringRef Code,
                                const std::optional<FormatStyle> &Style = {}) {
     testing::ScopedTrace t(File, Line, ::testing::Message() << Code.str());
-    EXPECT_EQ(Code.str(),
-              format(test::messUp(Code), Style, SC_ExpectIncomplete));
+    EXPECT_EQ(Code.str(), format(messUp(Code), Style, SC_ExpectIncomplete));
   }
 
   void
   _verifyIndependentOfContext(const char *File, int Line, llvm::StringRef Text,
                               const std::optional<FormatStyle> &Style = {}) {
     _verifyFormat(File, Line, Text, Style);
     _verifyFormat(File, Line, llvm::Twine("void f() { " + Text + " }").str(),
                   Style);
#define verifyIncompleteFormat(...)                                            \
   _verifyIncompleteFormat(__FILE__, __LINE__, __VA_ARGS__)
 #define verifyFormat(...) _verifyFormat(__FILE__, __LINE__, __VA_ARGS__)
 #define verifyGoogleFormat(Code) verifyFormat(Code, getGoogleStyle())
 
 } // namespace test
 } // namespace format
 } // namespace clang
 
-#endif
+#endif
 

clang/unittests/Format/FormatTestVerilog.cpp

 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#include "FormatTestUtils.h"
-#include "clang/Format/Format.h"
-#include "llvm/Support/Debug.h"
-#include "gtest/gtest.h"
+#include "FormatTestBase.h"
 
 #define DEBUG_TYPE "format-test"
 
 namespace clang {
 namespace format {
-
-class FormatTestVerilog : public ::testing::Test {
+namespace test {
+namespace {
+class FormatTestVerilog : public test::FormatTestBase {
 protected:
-  static std::string format(llvm::StringRef Code, unsigned Offset,
-                            unsigned Length, const FormatStyle &Style) {
-    LLVM_DEBUG(llvm::errs() << "---\n");
-    LLVM_DEBUG(llvm::errs() << Code << "\n\n");
-    std::vector<tooling::Range> Ranges(1, tooling::Range(Offset, Length));
-    tooling::Replacements Replaces = reformat(Style, Code, Ranges);
-    auto Result = applyAllReplacements(Code, Replaces);
-    EXPECT_TRUE(static_cast<bool>(Result));
-    LLVM_DEBUG(llvm::errs() << "\n" << *Result << "\n\n");
-    return *Result;
-  }
-
-  static std::string
-  format(llvm::StringRef Code,
-         const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) {
-    return format(Code, 0, Code.size(), Style);
-  }
-
-  static void verifyFormat(
-      llvm::StringRef Code,
-      const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) {
-    EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable";
-    EXPECT_EQ(Code.str(),
-              format(test::messUp(Code, /*HandleHash=*/false), Style));
+  virtual FormatStyle getDefaultStyle() const override {
+    return getLLVMStyle(FormatStyle::LK_Verilog);
+  }
+  virtual std::string messUp(llvm::StringRef Code) const override {
+    return test::messUp(Code, /*HandleHash=*/false);
   }
 };
 
 TEST_F(FormatTestVerilog, Align) {
-  FormatStyle Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  FormatStyle Style = getDefaultStyle();
   Style.AlignConsecutiveAssignments.Enabled = true;
   verifyFormat("x            <= x;\n"
                "sfdbddfbdfbb <= x;\n"
                "x             = x;",
                Style);
   verifyFormat("x            = x;\n"
                "sfdbddfbdfbb = x;\n"
                "x            = x;",
verifyFormat("case (data)\n"
                "  8'b1???????:\n"
                "    instruction1(ir);\n"
                "endcase");
   verifyFormat("case (data)\n"
                "  x ? 8'b1??????? : 1:\n"
                "    instruction3(ir);\n"
                "endcase");
   // Test indention options.
-  auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  auto Style = getDefaultStyle();
   Style.IndentCaseLabels = false;
   verifyFormat("case (data)\n"
                "16'd0:\n"
                "  result = 10'b0111111111;\n"
                "endcase",
                Style);
   verifyFormat("case (data)\n"
                "16'd0: begin\n"
verifyFormat("case (data)\n"
                Style);
   verifyFormat("case (data)\n"
                "  16'd0: begin\n"
                "    result = 10'b0111111111;\n"
                "  end\n"
                "endcase",
                Style);
   // Other colons should not be mistaken as case colons.
-  Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  Style = getDefaultStyle();
   Style.BitFieldColonSpacing = FormatStyle::BFCS_None;
   verifyFormat("case (x[1:0])\n"
                "endcase",
                Style);
   verifyFormat("default:\n"
                "  x[1:0] = x[1:0];",
                Style);
   Style.BitFieldColonSpacing = FormatStyle::BFCS_Both;
   verifyFormat("case (x[1 : 0])\n"
                "endcase",
                Style);
   verifyFormat("default:\n"
                "  x[1 : 0] = x[1 : 0];",
                Style);
-  Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  Style = getDefaultStyle();
   Style.SpacesInContainerLiterals = true;
   verifyFormat("case ('{x : x, default : 9})\n"
                "endcase",
                Style);
   verifyFormat("x = '{x : x, default : 9};\n", Style);
   verifyFormat("default:\n"
                "  x = '{x : x, default : 9};\n",
                Style);
TEST_F(FormatTestVerilog, Delay) {
   verifyFormat("#1us;");
   verifyFormat("#1.5us;");
   verifyFormat("#1ms;");
   verifyFormat("#1.5ms;");
   verifyFormat("#1s;");
   verifyFormat("#1.5s;");
   // The following expression should be on the same line.
   verifyFormat("#1 x = x;");
-  EXPECT_EQ("#1 x = x;", format("#1\n"
-                                "x = x;"));
+  verifyFormat("#1 x = x;", "#1\n"
+                            "x = x;");
 }
 
 TEST_F(FormatTestVerilog, Headers) {
   // Test headers with multiple ports.
   verifyFormat("module mh1\n"
                "    (input var int in1,\n"
                "     input var shortreal in2,\n"
                "     output tagged_st out);\n"
TEST_F(FormatTestVerilog, Headers) {
   verifyFormat("module m\n"
                "    (input var x `a, b);\n"
                "endmodule");
   verifyFormat("module m\n"
                "    (input var x `a, //\n"
                "                 b);\n"
                "endmodule");
   // With a concatenation in the names.
-  auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  auto Style = getDefaultStyle();
   Style.ColumnLimit = 40;
   verifyFormat("`define X(x)                           \\\n"
                "  module test                          \\\n"
                "      (input var x``x a, b);",
                Style);
   verifyFormat("`define X(x)                           \\\n"
                "  module test                          \\\n"
                "      (input var x``x aaaaaaaaaaaaaaa, \\\n"
verifyFormat("virtual class x\n"
                "endclass : x\n");
   verifyFormat("function automatic logic [1 : 0] x\n"
                "    (input x);\n"
                "  generate\n"
                "  endgenerate\n"
                "endfunction : x");
 }
 
+TEST_F(FormatTestVerilog, Identifiers) {
+  // Escaped identifiers should not be split.
+  verifyFormat("\\busa+index");
+  verifyFormat("\\-clock");
+  verifyFormat("\\***error-condition***");
+  verifyFormat("\\net1\\/net2");
+  verifyFormat("\\{a,b}");
+  verifyFormat("\\a*(b+c)");
+  // Escaped identifiers can't be joined with the next token.  Extra space
+  // should be removed.
+  verifyFormat("\\busa+index ;", "\\busa+index\n"
+                                 ";");
+  verifyFormat("\\busa+index ;", "\\busa+index\r\n"
+                                 ";");
+  verifyFormat("\\busa+index ;", "\\busa+index  ;");
+  verifyFormat("\\busa+index ;", "\\busa+index\n"
+                                 " ;");
+  verifyFormat("\\busa+index ;");
+  verifyFormat("(\\busa+index );");
+  verifyFormat("\\busa+index \\busa+index ;");
+}
+
 TEST_F(FormatTestVerilog, If) {
   verifyFormat("if (x)\n"
                "  x = x;");
   verifyFormat("unique if (x)\n"
                "  x = x;");
   verifyFormat("unique0 if (x)\n"
                "  x = x;");
   verifyFormat("priority if (x)\n"
TEST_F(FormatTestVerilog, Operators) {
   verifyFormat("x |= x;");
   verifyFormat("x <<= x;");
   verifyFormat("x >>= x;");
   verifyFormat("x <<<= x;");
   verifyFormat("x >>>= x;");
   verifyFormat("x <= x;");
 
   // Test that space is added between operators.
-  EXPECT_EQ("x = x < -x;", format("x=x<-x;"));
-  EXPECT_EQ("x = x << -x;", format("x=x<<-x;"));
-  EXPECT_EQ("x = x <<< -x;", format("x=x<<<-x;"));
+  verifyFormat("x = x < -x;", "x=x<-x;");
+  verifyFormat("x = x << -x;", "x=x<<-x;");
+  verifyFormat("x = x <<< -x;", "x=x<<<-x;");
 }
 
 TEST_F(FormatTestVerilog, Preprocessor) {
-  auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  auto Style = getDefaultStyle();
   Style.ColumnLimit = 20;
 
   // Macro definitions.
-  EXPECT_EQ("`define X          \\\n"
+  verifyFormat("`define X          \\\n"
                "  if (x)           \\\n"
                "    x = x;",
-            format("`define X if(x)x=x;", Style));
-  EXPECT_EQ("`define X(x)       \\\n"
+               "`define X if(x)x=x;", Style);
+  verifyFormat("`define X(x)       \\\n"
                "  if (x)           \\\n"
                "    x = x;",
-            format("`define X(x) if(x)x=x;", Style));
-  EXPECT_EQ("`define X          \\\n"
+               "`define X(x) if(x)x=x;", Style);
+  verifyFormat("`define X          \\\n"
                "  x = x;           \\\n"
                "  x = x;",
-            format("`define X x=x;x=x;", Style));
+               "`define X x=x;x=x;", Style);
   // Macro definitions with invocations inside.
-  EXPECT_EQ("`define LIST       \\\n"
+  verifyFormat("`define LIST       \\\n"
                "  `ENTRY           \\\n"
                "  `ENTRY",
-            format("`define LIST \\\n"
-                   "`ENTRY \\\n"
-                   "`ENTRY",
-                   Style));
-  EXPECT_EQ("`define LIST       \\\n"
+               "`define LIST \\\n"
+               Style);
+  verifyFormat("`define LIST       \\\n"
                "  `x = `x;         \\\n"
                "  `x = `x;",
-            format("`define LIST \\\n"
-                   "`x = `x; \\\n"
-                   "`x = `x;",
-                   Style));
-  EXPECT_EQ("`define LIST       \\\n"
+               "`define LIST \\\n"
+               Style);
+  verifyFormat("`define LIST       \\\n"
                "  `x = `x;         \\\n"
                "  `x = `x;",
-            format("`define LIST `x=`x;`x=`x;", Style));
+               "`define LIST `x=`x;`x=`x;", Style);
   // Macro invocations.
   verifyFormat("`x = (`x1 + `x2 + x);");
   // Lines starting with a preprocessor directive should not be indented.
   std::string Directives[] = {
       "begin_keywords",
       "celldefine",
       "default_nettype",
       "define",
std::string Directives[] = {
       "pragma",
       "resetall",
       "timescale",
       "unconnected_drive",
       "undef",
       "undefineall",
   };
   for (auto &Name : Directives) {
-    EXPECT_EQ("if (x)\n"
+    verifyFormat("if (x)\n"
                  "`" +
                      Name +
                      "\n"
                      "  ;",
-              format("if (x)\n"
-                     "`" +
-                         Name +
-                         "\n"
-                         ";",
-                     Style));
+                 "if (x)\n"
+                 Style);
   }
   // Lines starting with a regular macro invocation should be indented as a
   // normal line.
-  EXPECT_EQ("if (x)\n"
+  verifyFormat("if (x)\n"
                "  `x = `x;\n"
                "`timescale 1ns / 1ps",
-            format("if (x)\n"
-                   "`x = `x;\n"
-                   "`timescale 1ns / 1ps",
-                   Style));
-  EXPECT_EQ("if (x)\n"
+               "if (x)\n"
+               Style);
+  verifyFormat("if (x)\n"
                "`timescale 1ns / 1ps\n"
                "  `x = `x;",
-            format("if (x)\n"
-                   "`timescale 1ns / 1ps\n"
-                   "`x = `x;",
-                   Style));
+               "if (x)\n"
+               Style);
   std::string NonDirectives[] = {
       // For `__FILE__` and `__LINE__`, although the standard classifies them as
       // preprocessor directives, they are used like regular macros.
       "__FILE__", "__LINE__", "elif", "foo", "x",
   };
   for (auto &Name : NonDirectives) {
-    EXPECT_EQ("if (x)\n"
+    verifyFormat("if (x)\n"
                  "  `" +
                      Name + ";",
-              format("if (x)\n"
-                     "`" +
-                         Name +
-                         "\n"
-                         ";",
-                     Style));
+                 "if (x)\n"
+                 Style);
   }
 }
 
 TEST_F(FormatTestVerilog, Primitive) {
   verifyFormat("primitive multiplexer\n"
                "    (mux, control, dataA, dataB);\n"
                "  output mux;\n"
                "  input control, dataA, dataB;\n"
verifyFormat("always_ff @(posedge x)\n"
                "  x <= x;");
   verifyFormat("initial\n"
                "  x <= x;");
   verifyFormat("final\n"
                "  x <= x;");
   verifyFormat("forever\n"
                "  x <= x;");
 }
+} // namespace
+} // namespace test
 } // namespace format
-} // end namespace clang
+} // namespace clang