[SystemZ] Allow any I5 in RotateSelect*

[iii]

Summary

For all RotateSelect* instructions, PoP says:

Bits 0-1 of the I5 field (bits 32-33 of the instruction) are
ignored.

LLVM, however, completely prohibits using them, e.g.:

error: invalid operand for instruction
asm("rxsbg %[r1],%[r2],177,43,228\n"

Lift this unnecessary restriction.

[uweigand]

I believe the imm32zx6 operand definition is now unused and should be removed as well. Otherwise this LGTM.

[iii]

• Drop imm32zx6.

[uweigand]

LGTM, thanks!

[iii]

This now causes: https://lab.llvm.org/buildbot/#/builders/57/builds/25796

/home/buildbots/docker-RHEL84-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp:209:21: error: unused function 'decodeU6ImmOperand' [-Werror,-Wunused-function]
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
                    ^
1 error generated.

I will fix it.

[iii]

https://reviews.llvm.org/D147521

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

let DispSize = "20" in
       def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
   }
 }
 
 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
                        RegisterOperand cls2>
   : InstRIEf<opcode, (outs cls1:$R1),
              (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
-                  imm32zx6:$I5),
+                  imm32zx8:$I5),
              mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
   : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
              mnemonic#"\t$M1, $XBD2",
class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
   let AccessBytes = bytes;
 }
 
 // Like RotateSelectRIEf, but expanded after RA depending on the choice
 // of registers.
 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
   : Pseudo<(outs cls1:$R1),
            (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
-                imm32zx6:$I5),
+                imm32zx8:$I5),
            []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
 // the value of the PSW's 2-bit condition code field.
 class SelectWrapper<ValueType vt, RegisterOperand cls>
: Alias<4, (outs), (ins cls:$R1, imm:$I2),
           [(set CC, (operator cls:$R1, imm:$I2))]> {
   let isCompare = 1;
 }
 
 // An alias of a RotateSelectRIEf, but with different register sizes.
 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
   : Alias<6, (outs cls1:$R1),
           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
-               imm32zx6:$I5), []> {
+               imm32zx8:$I5), []> {
   let Constraints = "$R1 = $R1src";
 }
 
 class MemsetPseudo<DAGOperand lenop, DAGOperand byteop>
   : Pseudo<(outs), (ins bdaddr12only:$dest, lenop:$length, byteop:$B),
            [(z_memset_mvc bdaddr12only:$dest, lenop:$length, byteop:$B)]> {
   let Defs = [CC];
   let mayLoad = 1;

llvm/lib/Target/SystemZ/SystemZOperands.td

 }], NOOP_SDNodeXForm, "U4Imm">;
 
 // Note: this enforces an even value during code generation only.
 // When used from the assembler, any 4-bit value is allowed.
 defm imm32zx4even : Immediate<i32, [{
   return isUInt<4>(N->getZExtValue());
 }], UIMM8EVEN, "U4Imm">;
 
-defm imm32zx6 : Immediate<i32, [{
-  return isUInt<6>(N->getZExtValue());
-}], NOOP_SDNodeXForm, "U6Imm">;
-
 defm imm32sx8 : Immediate<i32, [{
   return isInt<8>(N->getSExtValue());
 }], SIMM8, "S8Imm">;
 
 defm imm32zx8 : Immediate<i32, [{
   return isUInt<8>(N->getZExtValue());
 }], UIMM8, "U8Imm">;
 

llvm/test/MC/SystemZ/insn-bad-z196.s

#CHECK: ppa %r4, %r6, 7
   ppa %r4, %r6, 7
 
 #CHECK: error: instruction requires: miscellaneous-extensions
 #CHECK: risbgn  %r1, %r2, 0, 0, 0
 
   risbgn  %r1, %r2, 0, 0, 0
 
 #CHECK: error: invalid operand
-#CHECK: risbhg  %r0,%r0,0,0,-1
-#CHECK: error: invalid operand
-#CHECK: risbhg  %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: risbhg  %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: risbhg  %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: risbhg  %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: risbhg  %r0,%r0,256,0,0
 
-  risbhg  %r0,%r0,0,0,-1
-  risbhg  %r0,%r0,0,0,64
   risbhg  %r0,%r0,0,-1,0
   risbhg  %r0,%r0,0,256,0
   risbhg  %r0,%r0,-1,0,0
   risbhg  %r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
-#CHECK: risblg  %r0,%r0,0,0,-1
-#CHECK: error: invalid operand
-#CHECK: risblg  %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: risblg  %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: risblg  %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: risblg  %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: risblg  %r0,%r0,256,0,0
 
-  risblg  %r0,%r0,0,0,-1
-  risblg  %r0,%r0,0,0,64
   risblg  %r0,%r0,0,-1,0
   risblg  %r0,%r0,0,256,0
   risblg  %r0,%r0,-1,0,0
   risblg  %r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
 #CHECK: sdtra %f0, %f0, %f0, -1
 #CHECK: error: invalid operand

llvm/test/MC/SystemZ/insn-bad-zEC12.s

#CHECK: ppa %r0, %r0, 16
   ppa %r0, %r0, 16
 
 #CHECK: error: instruction requires: message-security-assist-extension5
 #CHECK: ppno  %r2, %r4
 
   ppno  %r2, %r4
 
 #CHECK: error: invalid operand
-#CHECK: risbgn  %r0,%r0,0,0,-1
-#CHECK: error: invalid operand
-#CHECK: risbgn  %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: risbgn  %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: risbgn  %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: risbgn  %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: risbgn  %r0,%r0,256,0,0
 
-  risbgn  %r0,%r0,0,0,-1
-  risbgn  %r0,%r0,0,0,64
   risbgn  %r0,%r0,0,-1,0
   risbgn  %r0,%r0,0,256,0
   risbgn  %r0,%r0,-1,0,0
   risbgn  %r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
 #CHECK: tabort  -1
 #CHECK: error: invalid operand

llvm/test/MC/SystemZ/insn-bad.s

#CHECK: qsi 0(%r1,%r2)
 
   qsi -1
   qsi 4096
   qsi 0(%r1,%r2)
 
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,0,-1
 #CHECK: error: invalid operand
-#CHECK: risbg %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,256,0,0
 
   risbg  %r0,%r0,0,0,-1
-  risbg  %r0,%r0,0,0,64
   risbg  %r0,%r0,0,-1,0
   risbg  %r0,%r0,0,256,0
   risbg  %r0,%r0,-1,0,0
   risbg  %r0,%r0,256,0,0
 
 #CHECK: error: instruction requires: high-word
 #CHECK: risbhg  %r1, %r2, 0, 0, 0
 

 #CHECK: error: invalid use of indexed addressing
 #CHECK: rllg  %r0,%r0,0(%r1,%r2)
 
   rllg  %r0,%r0,-524289
   rllg  %r0,%r0,524288
   rllg  %r0,%r0,0(%r1,%r2)
 
 #CHECK: error: invalid operand
-#CHECK: rnsbg %r0,%r0,0,0,-1
-#CHECK: error: invalid operand
-#CHECK: rnsbg %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: rnsbg %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: rnsbg %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: rnsbg %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: rnsbg %r0,%r0,256,0,0
 
-  rnsbg  %r0,%r0,0,0,-1
-  rnsbg  %r0,%r0,0,0,64
   rnsbg  %r0,%r0,0,-1,0
   rnsbg  %r0,%r0,0,256,0
   rnsbg  %r0,%r0,-1,0,0
   rnsbg  %r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
-#CHECK: rosbg %r0,%r0,0,0,-1
-#CHECK: error: invalid operand
-#CHECK: rosbg %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: rosbg %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: rosbg %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: rosbg %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: rosbg %r0,%r0,256,0,0
 
-  rosbg  %r0,%r0,0,0,-1
-  rosbg  %r0,%r0,0,0,64
   rosbg  %r0,%r0,0,-1,0
   rosbg  %r0,%r0,0,256,0
   rosbg  %r0,%r0,-1,0,0
   rosbg  %r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
 #CHECK: rp  -1
 #CHECK: error: invalid operand
#CHECK: rrxtr %f2, %f0, %f0, 0
 
   rrxtr %f0, %f0, %f0, -1
   rrxtr %f0, %f0, %f0, 16
   rrxtr %f0, %f0, %f2, 0
   rrxtr %f0, %f2, %f0, 0
   rrxtr %f2, %f0, %f0, 0
 
 #CHECK: error: invalid operand
-#CHECK: rxsbg %r0,%r0,0,0,-1
-#CHECK: error: invalid operand
-#CHECK: rxsbg %r0,%r0,0,0,64
-#CHECK: error: invalid operand
 #CHECK: rxsbg %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: rxsbg %r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: rxsbg %r0,%r0,-1,0,0
 #CHECK: error: invalid operand
 #CHECK: rxsbg %r0,%r0,256,0,0
 
-  rxsbg  %r0,%r0,0,0,-1
-  rxsbg  %r0,%r0,0,0,64
   rxsbg  %r0,%r0,0,-1,0
   rxsbg  %r0,%r0,0,256,0
   rxsbg  %r0,%r0,-1,0,0
   rxsbg  %r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
 #CHECK: s %r0, -1
 #CHECK: error: invalid operand

llvm/test/MC/SystemZ/insn-good-z196.s

#CHECK: popcnt  %r7, %r8                # encoding: [0xb9,0xe1,0x00,0x78]
 
   popcnt  %r0,%r0
   popcnt  %r0,%r15
   popcnt  %r15,%r0
   popcnt  %r7,%r8
 
 #CHECK: risbhg  %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d]
 #CHECK: risbhg  %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d]
+#CHECK: risbhg  %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x5d]
+#CHECK: risbhg  %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x5d]
 #CHECK: risbhg  %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d]
 #CHECK: risbhg  %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x5d]
 #CHECK: risbhg  %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x5d]
 #CHECK: risbhg  %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x5d]
 #CHECK: risbhg  %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x5d]
 
   risbhg  %r0,%r0,0,0,0
   risbhg  %r0,%r0,0,0,63
+  risbhg  %r0,%r0,0,0,64
+  risbhg  %r0,%r0,0,0,255
   risbhg  %r0,%r0,0,255,0
   risbhg  %r0,%r0,255,0,0
   risbhg  %r0,%r15,0,0,0
   risbhg  %r15,%r0,0,0,0
   risbhg  %r4,%r5,6,7,8
 
 #CHECK: risblg  %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x51]
 #CHECK: risblg  %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x51]
+#CHECK: risblg  %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x51]
+#CHECK: risblg  %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x51]
 #CHECK: risblg  %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x51]
 #CHECK: risblg  %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x51]
 #CHECK: risblg  %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x51]
 #CHECK: risblg  %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x51]
 #CHECK: risblg  %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x51]
 
   risblg  %r0,%r0,0,0,0
   risblg  %r0,%r0,0,0,63
+  risblg  %r0,%r0,0,0,64
+  risblg  %r0,%r0,0,0,255
   risblg  %r0,%r0,0,255,0
   risblg  %r0,%r0,255,0,0
   risblg  %r0,%r15,0,0,0
   risblg  %r15,%r0,0,0,0
   risblg  %r4,%r5,6,7,8
 
 #CHECK: rrbm  %r0, %r0                # encoding: [0xb9,0xae,0x00,0x00]
 #CHECK: rrbm  %r0, %r15               # encoding: [0xb9,0xae,0x00,0x0f]

llvm/test/MC/SystemZ/insn-good-zEC12.s

#CHECK: ppa %r15, %r0, 0            # encoding: [0xb2,0xe8,0x00,0xf0]
   ppa %r0, %r0, 0
   ppa %r0, %r0, 15
   ppa %r0, %r15, 0
   ppa %r4, %r6, 7
   ppa %r15, %r0, 0
 
 #CHECK: risbgn  %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
 #CHECK: risbgn  %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
+#CHECK: risbgn  %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x59]
+#CHECK: risbgn  %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x59]
 #CHECK: risbgn  %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
 #CHECK: risbgn  %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x59]
 #CHECK: risbgn  %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59]
 #CHECK: risbgn  %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x59]
 #CHECK: risbgn  %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x59]
 
   risbgn  %r0,%r0,0,0,0
   risbgn  %r0,%r0,0,0,63
+  risbgn  %r0,%r0,0,0,64
+  risbgn  %r0,%r0,0,0,255
   risbgn  %r0,%r0,0,255,0
   risbgn  %r0,%r0,255,0,0
   risbgn  %r0,%r15,0,0,0
   risbgn  %r15,%r0,0,0,0
   risbgn  %r4,%r5,6,7,8
 
 #CHECK: tabort  0                       # encoding: [0xb2,0xfc,0x00,0x00]
 #CHECK: tabort  0(%r1)                  # encoding: [0xb2,0xfc,0x10,0x00]

llvm/test/MC/SystemZ/insn-good.s

#CHECK: qsi 4095(%r15)              # encoding: [0xb2,0x86,0xff,0xff]
   qsi 4095(%r15)
 
 #CHECK: rchp                            # encoding: [0xb2,0x3b,0x00,0x00]
 
   rchp
 
 #CHECK: risbg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
 #CHECK: risbg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
+#CHECK: risbg %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x55]
+#CHECK: risbg %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x55]
 #CHECK: risbg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
 #CHECK: risbg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
 #CHECK: risbg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55]
 #CHECK: risbg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55]
 #CHECK: risbg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
 
   risbg %r0,%r0,0,0,0
   risbg %r0,%r0,0,0,63
+  risbg %r0,%r0,0,0,64
+  risbg %r0,%r0,0,0,255
   risbg %r0,%r0,0,255,0
   risbg %r0,%r0,255,0,0
   risbg %r0,%r15,0,0,0
   risbg %r15,%r0,0,0,0
   risbg %r4,%r5,6,7,8
 
 #CHECK: rll %r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0x1d]
 #CHECK: rll %r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x1d]
#CHECK: rllg  %r0, %r0, 524287(%r15)  # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x1c]
   rllg  %r0,%r0,524287
   rllg  %r0,%r0,0(%r1)
   rllg  %r0,%r0,0(%r15)
   rllg  %r0,%r0,524287(%r1)
   rllg  %r0,%r0,524287(%r15)
 
 #CHECK: rnsbg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x54]
 #CHECK: rnsbg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x54]
+#CHECK: rnsbg %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x54]
+#CHECK: rnsbg %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x54]
 #CHECK: rnsbg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x54]
 #CHECK: rnsbg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x54]
 #CHECK: rnsbg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x54]
 #CHECK: rnsbg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x54]
 #CHECK: rnsbg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x54]
 
   rnsbg %r0,%r0,0,0,0
   rnsbg %r0,%r0,0,0,63
+  rnsbg %r0,%r0,0,0,64
+  rnsbg %r0,%r0,0,0,255
   rnsbg %r0,%r0,0,255,0
   rnsbg %r0,%r0,255,0,0
   rnsbg %r0,%r15,0,0,0
   rnsbg %r15,%r0,0,0,0
   rnsbg %r4,%r5,6,7,8
 
 #CHECK: rosbg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x56]
 #CHECK: rosbg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x56]
+#CHECK: rosbg %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x56]
+#CHECK: rosbg %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x56]
 #CHECK: rosbg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x56]
 #CHECK: rosbg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x56]
 #CHECK: rosbg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x56]
 #CHECK: rosbg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x56]
 #CHECK: rosbg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x56]
 
   rosbg %r0,%r0,0,0,0
   rosbg %r0,%r0,0,0,63
+  rosbg %r0,%r0,0,0,64
+  rosbg %r0,%r0,0,0,255
   rosbg %r0,%r0,0,255,0
   rosbg %r0,%r0,255,0,0
   rosbg %r0,%r15,0,0,0
   rosbg %r15,%r0,0,0,0
   rosbg %r4,%r5,6,7,8
 
 #CHECK: rp  0                       # encoding: [0xb2,0x77,0x00,0x00]
 #CHECK: rp  0(%r1)                  # encoding: [0xb2,0x77,0x10,0x00]
#CHECK: rrxtr %f13, %f0, %f0, 0       # encoding: [0xb3,0xff,0x00,0xd0]
   rrxtr %f13, %f0, %f0, 0
 
 #CHECK: rsch                            # encoding: [0xb2,0x38,0x00,0x00]
 
   rsch
 
 #CHECK: rxsbg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x57]
 #CHECK: rxsbg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x57]
+#CHECK: rxsbg %r0, %r0, 0, 0, 64      # encoding: [0xec,0x00,0x00,0x00,0x40,0x57]
+#CHECK: rxsbg %r0, %r0, 0, 0, 255     # encoding: [0xec,0x00,0x00,0x00,0xff,0x57]
 #CHECK: rxsbg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x57]
 #CHECK: rxsbg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x57]
 #CHECK: rxsbg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x57]
 #CHECK: rxsbg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x57]
 #CHECK: rxsbg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x57]
 
   rxsbg %r0,%r0,0,0,0
   rxsbg %r0,%r0,0,0,63
+  rxsbg %r0,%r0,0,0,64
+  rxsbg %r0,%r0,0,0,255
   rxsbg %r0,%r0,0,255,0
   rxsbg %r0,%r0,255,0,0
   rxsbg %r0,%r15,0,0,0
   rxsbg %r15,%r0,0,0,0
   rxsbg %r4,%r5,6,7,8
 
 #CHECK: s %r0, 0                  # encoding: [0x5b,0x00,0x00,0x00]
 #CHECK: s %r0, 4095               # encoding: [0x5b,0x00,0x0f,0xff]