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Differential D14612

[mips] Use multiclass patterns for f32/f64 comparisons and i32 selects.
ClosedPublic

Authored by vkalintiris on Nov 12 2015, 4:55 AM.

Details

Reviewers
dsanders
Commits
rGddf7e6885a91: [mips] Use multiclass patterns for f32/f64 comparisons and i32 selects.
rL255110: [mips] Use multiclass patterns for f32/f64 comparisons and i32 selects.
Summary

Although the multiclass for i32 selects might seem redundant as it has
only one instantiation, we will use it to replace the correspondent
patterns in Mips64r6InstrInfo.td in follow-up commits.

Diff Detail

Event Timeline

vkalintiris updated this revision to Diff 40034.Nov 12 2015, 4:55 AM
vkalintiris retitled this revision from to [mips] Use multiclass patterns for f32/f64 comparisons and i32 selects..
vkalintiris updated this object.
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptNov 12 2015, 4:55 AM
vkalintiris added a child revision: D10970: [mips] Promote the result of SETCC nodes to GPR width..Nov 30 2015, 8:25 AM
vkalintiris mentioned this in D15047: [Mips64] Fix extension of 32-bit integer types..
dsanders added a child revision: D15047: [Mips64] Fix extension of 32-bit integer types..Nov 30 2015, 8:45 AM
dsanders removed a child revision: D15047: [Mips64] Fix extension of 32-bit integer types..Nov 30 2015, 8:47 AM
dsanders accepted this revision.Dec 8 2015, 3:37 AM
dsanders edited edge metadata.

LGTM with a nit.

lib/Target/Mips/Mips32r6InstrInfo.td
791

'RC' normally means 'RegisterClass' in these files. Could you pick another name?

This revision is now accepted and ready to land.Dec 8 2015, 3:37 AM
Closed by commit rL255110: [mips] Use multiclass patterns for f32/f64 comparisons and i32 selects. (authored by vkalintiris). · Explain WhyDec 9 2015, 5:27 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
144 lines

Diff 40034

lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6; def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Patterns and Pseudo Instructions // Patterns and Pseudo Instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// f32 comparisons supported via another comparison // comparisons supported via another comparison
def : MipsPat<(setone f32:$lhs, f32:$rhs), multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
(NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; def : MipsPat<(setone VT:$lhs, VT:$rhs),
def : MipsPat<(seto f32:$lhs, f32:$rhs), (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
(NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; def : MipsPat<(seto VT:$lhs, VT:$rhs),
def : MipsPat<(setune f32:$lhs, f32:$rhs), (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
(NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; def : MipsPat<(setune VT:$lhs, VT:$rhs),
def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>, (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
ISA_MIPS32R6; def : MipsPat<(seteq VT:$lhs, VT:$rhs),
def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>, (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>;
ISA_MIPS32R6; def : MipsPat<(setgt VT:$lhs, VT:$rhs),
def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>, (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>;
ISA_MIPS32R6; def : MipsPat<(setge VT:$lhs, VT:$rhs),
def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_LT_S f32:$lhs, f32:$rhs)>, (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>;
ISA_MIPS32R6; def : MipsPat<(setlt VT:$lhs, VT:$rhs),
def : MipsPat<(setle f32:$lhs, f32:$rhs), (CMP_LE_S f32:$lhs, f32:$rhs)>, (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>;
ISA_MIPS32R6; def : MipsPat<(setle VT:$lhs, VT:$rhs),
def : MipsPat<(setne f32:$lhs, f32:$rhs), (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>;
(NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; def : MipsPat<(setne VT:$lhs, VT:$rhs),
(NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
}
// f64 comparisons supported via another comparison defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
def : MipsPat<(setone f64:$lhs, f64:$rhs), defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
(NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
def : MipsPat<(seto f64:$lhs, f64:$rhs),
(NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
def : MipsPat<(setune f64:$lhs, f64:$rhs),
(NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
ISA_MIPS32R6;
def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
ISA_MIPS32R6;
def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_LT_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
def : MipsPat<(setle f64:$lhs, f64:$rhs), (CMP_LE_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
def : MipsPat<(setne f64:$lhs, f64:$rhs),
(NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
// i32 selects // i32 selects
multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,
dsandersUnsubmitted
Not Done
ReplyInline Actions

'RC' normally means 'RegisterClass' in these files. Could you pick another name?

dsanders: 'RC' normally means 'RegisterClass' in these files. Could you pick another name?
Instruction SLTiOp, Instruction SLTiuOp,
Instruction SELEQZOp, Instruction SELNEZOp,
SDPatternOperator imm_type, ValueType VT> {
// reg, immz
def : MipsPat<(select (VT (seteq RC:$cond, immz)), RC:$t, RC:$f),
(OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>;
def : MipsPat<(select (VT (setne RC:$cond, immz)), RC:$t, RC:$f),
(OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>;
// reg, immZExt16[_64]
def : MipsPat<(select (VT (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
(OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
(SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
def : MipsPat<(select (VT (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
(OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
(SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
// reg, immSExt16Plus1
def : MipsPat<(select (VT (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
(OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))),
(SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>;
def : MipsPat<(select (VT (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
(OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))),
(SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
def : MipsPat<(select (VT (seteq RC:$cond, immz)), RC:$t, immz),
(SELEQZOp RC:$t, RC:$cond)>;
def : MipsPat<(select (VT (setne RC:$cond, immz)), RC:$t, immz),
(SELNEZOp RC:$t, RC:$cond)>;
def : MipsPat<(select (VT (seteq RC:$cond, immz)), immz, RC:$f),
(SELNEZOp RC:$f, RC:$cond)>;
def : MipsPat<(select (VT (setne RC:$cond, immz)), immz, RC:$f),
(SELEQZOp RC:$f, RC:$cond)>;
}
defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
immZExt16, i32>, ISA_MIPS32R6;
def : MipsPat<(select i32:$cond, i32:$t, i32:$f), def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
(OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>, (OR (SELNEZ i32:$t, i32:$cond),
ISA_MIPS32R6; (SELEQZ i32:$f, i32:$cond))>,
def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
(OR (SELEQZ i32:$t, i32:$cond), (SELNEZ i32:$f, i32:$cond))>,
ISA_MIPS32R6;
def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
(OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
ISA_MIPS32R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
(OR (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
(SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
ISA_MIPS32R6;
def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
(OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
(SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
ISA_MIPS32R6; ISA_MIPS32R6;
def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
i32:$f),
(OR (SELEQZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
(SELNEZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
ISA_MIPS32R6;
def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
i32:$t, i32:$f),
(OR (SELEQZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
(SELNEZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
ISA_MIPS32R6;
def : MipsPat<(select i32:$cond, i32:$t, immz), def : MipsPat<(select i32:$cond, i32:$t, immz),
(SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6; (SELNEZ i32:$t, i32:$cond)>,
def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz), ISA_MIPS32R6;
(SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
(SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
def : MipsPat<(select i32:$cond, immz, i32:$f), def : MipsPat<(select i32:$cond, immz, i32:$f),
(SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6; (SELEQZ i32:$f, i32:$cond)>,
def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f), ISA_MIPS32R6;
(SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
(SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;