[BOLT][NFC] Simplify MCPlusBuilder::getRegSize

[Amir]

Summary

Pre-calculate the register size table in MCPlusBuilder constructor,
similar to AliasMap/SmallerAliasMap in initAliases.

[Amir]

clang-format

[rafauler]

LGTM

bolt/include/bolt/Core/MCPlusBuilder.h

public:
   MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info,
                 const MCRegisterInfo *RegInfo)
       : Analysis(Analysis), Info(Info), RegInfo(RegInfo) {
     // Initialize the default annotation allocator with id 0
     AnnotationAllocators.emplace(0, AnnotationAllocator());
     MaxAllocatorId++;
     // Build alias map
     initAliases();
+    initSizeMap();
   }
 
   /// Create and return target-specific MC symbolizer for the \p Function.
   virtual std::unique_ptr<MCSymbolizer>
   createTargetSymbolizer(BinaryFunction &Function) const {
     return nullptr;
   }
 
public:
   }
 
   /// Return a BitVector marking all sub or super registers of \p Reg, including
   /// itself.
   virtual const BitVector &getAliases(MCPhysReg Reg,
                                       bool OnlySmaller = false) const;
 
   /// Initialize aliases tables.
-  virtual void initAliases();
+  void initAliases();
+
+  /// Initialize register size table.
+  void initSizeMap();
 
   /// Change \p Regs setting all registers used to pass parameters according
   /// to the host abi. Do nothing if not implemented.
   virtual BitVector getRegsUsedAsParams() const {
     llvm_unreachable("not implemented");
     return BitVector();
   }
 
public:
   }
 
   /// Set of Registers used by the Rep instruction
   virtual void getRepRegs(BitVector &Regs) const {
     llvm_unreachable("not implemented");
   }
 
   /// Return the register width in bytes (1, 2, 4 or 8)
-  virtual uint8_t getRegSize(MCPhysReg Reg) const;
+  uint8_t getRegSize(MCPhysReg Reg) const { return SizeMap[Reg]; }
 
   /// For aliased registers, return an alias of \p Reg that has the width of
   /// \p Size bytes
   virtual MCPhysReg getAliasSized(MCPhysReg Reg, uint8_t Size) const {
     llvm_unreachable("not implemented");
     return 0;
   }
 
virtual BlocksVectorTy jumpTablePromotion(
     llvm_unreachable("not implemented");
     return BlocksVectorTy();
   }
 
   // AliasMap caches a mapping of registers to the set of registers that
   // alias (are sub or superregs of itself, including itself).
   std::vector<BitVector> AliasMap;
   std::vector<BitVector> SmallerAliasMap;
+  // SizeMap caches a mapping of registers to their sizes.
+  std::vector<uint8_t> SizeMap;
 };
 
 MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *,
                                       const MCInstrInfo *,
                                       const MCRegisterInfo *);
 
 MCPlusBuilder *createAArch64MCPlusBuilder(const MCInstrAnalysis *,
                                           const MCInstrInfo *,
                                           const MCRegisterInfo *);
 
 } // namespace bolt
 } // namespace llvm
 
 #endif

bolt/lib/Core/MCPlusBuilder.cpp

for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
         dbgs() << Idx << " ";
         Idx = BV.find_next(Idx);
       }
       dbgs() << "\n";
     }
   });
 }
 
-uint8_t MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
-  // SizeMap caches a mapping of registers to their sizes
-  static std::vector<uint8_t> SizeMap;
-
-  if (SizeMap.size() > 0) {
-    return SizeMap[Reg];
-  }
-  SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
+void MCPlusBuilder::initSizeMap() {
+  SizeMap.resize(RegInfo->getNumRegs());
   // Build size map
-  for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
-       ++I) {
-    for (MCPhysReg Reg : *I)
-      SizeMap[Reg] = I->getSizeInBits() / 8;
-  }
-
-  return SizeMap[Reg];
+  for (auto RC : RegInfo->regclasses())
+    for (MCPhysReg Reg : RC)
+      SizeMap[Reg] = RC.getSizeInBits() / 8;
 }
 
 bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
                                           const MCSymbol *Symbol,
                                           int64_t Addend, MCContext *Ctx,
                                           uint64_t RelType) const {
   MCOperand Operand;
   if (!Addend) {