Memory models for gfx90a and gfx940 do not require buffer_wbl2
before the fence for acquire ordering, but we do insert the full
release.
Fixes: SWDEV-386785
Details
Details
Diff Detail
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
| llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | ||
|---|---|---|
| 2212–2218 | Why is this waitcnt being added, I do not believe the memory model requires this. An acquire does not require previous memory operations to be complete. It only requires that the location being loaded has completed, followed by invalidating the caches consistent with the scope. | |
| llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | ||
|---|---|---|
| 2212–2218 | Memory model says this is the sequence: fence acquire - agent *none* 1. s_waitcnt lgkmcnt(0) &
vmcnt(0)And then the same for the rest of the fence cases. The code produced looks consistent with the memory model to me. | |
Comment Actions
After offline discussion, the extra waitcnt is needed because this is a fence, and an acquire needs a waitcnt to ensure a proceeding load atomic that pairs with the fence has completed before invalidating the cache. The memory model on AMDGPUUsage does show the extra waitcnt for the fence. Previously, the waitcnt was being generated as part of the release which is not required if the fence is just an acquire.
Why is this waitcnt being added, I do not believe the memory model requires this. An acquire does not require previous memory operations to be complete. It only requires that the location being loaded has completed, followed by invalidating the caches consistent with the scope.