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Differential D145134

[AArch64] Optimizing codegen for sign-extension
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Authored by nilanjana_basu on Mar 1 2023, 5:43 PM.
This is a draft revision that has not yet been submitted for review.

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Summary

Eliminating the redundant use of 'lsl' instruction by incorporating the logic in the already used 'sbfx' instruction.

Diff Detail

Unit TestsFailed

TimeTest
60,030 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test

Event Timeline

nilanjana_basu created this revision.Mar 1 2023, 5:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 1 2023, 5:43 PM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B216869: Diff 501708.Mar 1 2023, 6:43 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
5 lines
test/
CodeGen/
AArch64/
15 lines

Diff 501708

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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let AddedComplexity = 10 in { let AddedComplexity = 10 in {
def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)), def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
(SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)), def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
(SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
} }
let AddedComplexity = 21 in {
def : Pat<(i64 (sext (i32 (sra (i32 (shl GPR32:$Rn, (i64 imm0_31:$imm))), (i64 imm0_31:$imm))))),
(SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 0, (i64 (i32shift_b imm0_31:$imm)))>;
}
def : InstAlias<"asr $dst, $src, $shift", def : InstAlias<"asr $dst, $src, $shift",
(SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
def : InstAlias<"asr $dst, $src, $shift", def : InstAlias<"asr $dst, $src, $shift",
(SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
▲ Show 20 Lines • Show All 6,409 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/aarch64-combine-bit-operations.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
define i64 @sext_ashr_shl(i32 %x) {
; CHECK-LABEL: sext_ashr_shl:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, #23
; CHECK-NEXT: sbfx x0, x8, #23, #9
; CHECK-NEXT: ret
entry:
%bf.cast3 = shl i32 %x, 23
%bf.cast = ashr exact i32 %bf.cast3, 23
%conv = sext i32 %bf.cast to i64
ret i64 %conv
}