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Differential D144900

[X86] Add DwarfRegNums for segment registers
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Authored by abrachet on Feb 27 2023, 11:20 AM.

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pengfei
mcgrathr
Commits
rGf94fb2674805: [X86] Add DwarfRegNums for segment registers

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abrachet created this revision.Feb 27 2023, 11:20 AM
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mcgrathr added a subscriber: mcgrathr.Feb 27 2023, 11:29 AM

Needs a test case.

mcgrathr added inline comments.Feb 27 2023, 11:33 AM
llvm/lib/Target/X86/X86RegisterInfo.td
323

The comment above says this should be: [x86-64, x86-32 Darwin EH, generic x86-32].
So I think the -2 case is the middle one not the third one.

abrachet updated this revision to Diff 500877.Feb 27 2023, 12:34 PM
abrachet marked an inline comment as done.
abrachet added inline comments.
llvm/lib/Target/X86/X86RegisterInfo.td
323

Good catch, I had remembered this the other way around.

Harbormaster completed remote builds in B216282: Diff 500877.Feb 27 2023, 1:51 PM
mcgrathr accepted this revision.Feb 27 2023, 1:55 PM

lgtm

This revision is now accepted and ready to land.Feb 27 2023, 1:55 PM
Closed by commit rGf94fb2674805: [X86] Add DwarfRegNums for segment registers (authored by abrachet). · Explain WhyFeb 28 2023, 9:10 AM
This revision was automatically updated to reflect the committed changes.
abrachet marked an inline comment as done.
abrachet added a commit: rGf94fb2674805: [X86] Add DwarfRegNums for segment registers.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
12 lines

Diff 500855

llvm/lib/Target/X86/X86RegisterInfo.td

Show First 20 Lines • Show All 314 Lines • ▼ Show 20 Lines
def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>; def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>;
def RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>; def RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>;
// The direction flag. // The direction flag.
def DF : X86Reg<"dirflag", 0>; def DF : X86Reg<"dirflag", 0>;
// Segment registers // Segment registers
def CS : X86Reg<"cs", 1>; def CS : X86Reg<"cs", 1>, DwarfRegNum<[51, 41, -2]>;
mcgrathrUnsubmitted
Done
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The comment above says this should be: [x86-64, x86-32 Darwin EH, generic x86-32].
So I think the -2 case is the middle one not the third one.

mcgrathr: The comment above says this should be: [x86-64, x86-32 Darwin EH, generic x86-32]. So I think…
abrachetAuthorUnsubmitted
Done
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Good catch, I had remembered this the other way around.

abrachet: Good catch, I had remembered this the other way around.
def DS : X86Reg<"ds", 3>; def DS : X86Reg<"ds", 3>, DwarfRegNum<[53, 43, -2]>;
def SS : X86Reg<"ss", 2>; def SS : X86Reg<"ss", 2>, DwarfRegNum<[52, 42, -2]>;
def ES : X86Reg<"es", 0>; def ES : X86Reg<"es", 0>, DwarfRegNum<[50, 40, -2]>;
def FS : X86Reg<"fs", 4>; def FS : X86Reg<"fs", 4>, DwarfRegNum<[54, 44, -2]>;
def GS : X86Reg<"gs", 5>; def GS : X86Reg<"gs", 5>, DwarfRegNum<[55, 45, -2]>;
def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>; def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>;
def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>; def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>;
// Debug registers // Debug registers
def DR0 : X86Reg<"dr0", 0>; def DR0 : X86Reg<"dr0", 0>;
def DR1 : X86Reg<"dr1", 1>; def DR1 : X86Reg<"dr1", 1>;
def DR2 : X86Reg<"dr2", 2>; def DR2 : X86Reg<"dr2", 2>;
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