[AArch64] Update enabled extensions for Ampere1 core

[philipp.tomsich]

Summary

The original enablement for the Ampere1 core inadvertently had omitted
that FEAT_RAND is support and errorously claimed that FEAT_MTE was
available.

Adjust the definition of Ampere1 to match reality.

[dmgreen]

This looks like it might need a bit of a clang-format, but otherwise LGTM.

[philipp.tomsich]

v2:

• clang-format
• updated llvm/lib/Target/AArch64/AArch64.td to match

[philipp.tomsich]

Fix typo (AEK_AES4->AEK_AES).

llvm/include/llvm/TargetParser/AArch64TargetParser.h

inline constexpr CpuInfo CpuInfos[] = {
     {"tsv110", ARMV8_2A,
      (AArch64::AEK_CRYPTO | AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
       AArch64::AEK_FP16FML | AArch64::AEK_PROFILE)},
     {"a64fx", ARMV8_2A,
      (AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_SVE)},
     {"carmel", ARMV8_2A, (AArch64::AEK_CRYPTO | AArch64::AEK_FP16)},
     {"ampere1", ARMV8_6A,
      (AArch64::AEK_AES | AArch64::AEK_SHA2 | AArch64::AEK_SHA3 |
-      AArch64::AEK_FP16 | AArch64::AEK_SB | AArch64::AEK_SSBS)},
+      AArch64::AEK_FP16 | AArch64::AEK_SB | AArch64::AEK_SSBS |
+      AArch64::AEK_RAND)},
     // Invalid CPU
     {"invalid", INVALID, (AArch64::AEK_INVALID)},
 };
 
 // An alias for a CPU.
 struct CpuAlias {
   StringRef Alias;
   StringRef Name;

llvm/lib/Target/AArch64/AArch64.td

list<SubtargetFeature> ThunderX2T99  = [HasV8_1aOps, FeatureCRC, FeatureCrypto,
                                           FeatureFPARMv8, FeatureNEON, FeatureLSE];
   list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto,
                                           FeatureFPARMv8, FeatureNEON, FeatureLSE,
                                           FeaturePAuth, FeaturePerfMon];
   list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                    FeatureNEON, FeaturePerfMon, FeatureSPE,
                                    FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
   list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
-                                    FeatureMTE, FeatureSSBS];
+                                    FeatureSSBS, FeatureRandGen, FeatureSB,
+                                    FeatureSHA2, FeatureSHA3, FeatureAES];
 
   // ETE and TRBE are future architecture extensions. We temporarily enable them
   // by default for users targeting generic AArch64. The extensions do not
   // affect code generated by the compiler and can be used only by explicitly
   // mentioning the new system register names in assembly.
   list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
 }
 

llvm/unittests/TargetParser/TargetParserTest.cpp

::testing::Values(
                              AArch64::AEK_BF16 | AArch64::AEK_I8MM,
                          "8.5-A"),
         ARMCPUTestParams("ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
                          AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE     |
                              AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
                              AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 |
                              AArch64::AEK_AES  | AArch64::AEK_I8MM | AArch64::AEK_SSBS |
-                             AArch64::AEK_SB,
+                             AArch64::AEK_SB   | AArch64::AEK_RAND,
                          "8.6-A"),
         ARMCPUTestParams(
             "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
             AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
                 AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
                 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
                 AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
                 AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_BF16 |