[ARM] Accept shortened forms of the T2 ADC instruction

[JiruiWu]

Summary

The previous T2 ADC instruction requires three operands. This patch
supports its shortened forms.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrThumb2.td

1026–1027

Nit: It looks like PostISelHook needn't be a parameter if it is always passed 1.

[lenary]

llvm/lib/Target/ARM/ARMInstrThumb2.td

1026–1027

I wasn't sure if other instructions wanted to use T2I_adde_sube_irs without PostISelHook, even though none do right now, which is why i suggested this approach, but maybe the instruction definitions are now stable enough that this would be fine?

[dmgreen]

llvm/lib/Target/ARM/ARMInstrThumb2.td

1026–1027

It's not a big deal either way. Arm is fairly stable though, and if the parameter is needed by another patch I would suggest it should be simple enough to add there.

llvm/lib/Target/ARM/ARMInstrThumb2.td

def rs : T2sTwoRegShiftedReg<
      let Inst{24} = 1;
      let Inst{23-21} = op23_21;
    }
 }
 
 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
 /// for a binary operation that produces a value and use the carry
 /// bit. It's not predicable.
-let Defs = [CPSR], Uses = [CPSR] in {
 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
-                             bit Commutable = 0> {
+                             bit Commutable = 0, bit PostISelHook = 0> {
+  let Defs = [CPSR], Uses = [CPSR], hasPostISelHook = PostISelHook in {
    // shifted imm
    def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
                  IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
                [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
                  Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
def rs : T2sTwoRegShiftedReg<
                  (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
                  IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
          [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
                  Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
    }
   }
+  // Shortened forms
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
+     (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p,
+                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
+     (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
+                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $ShiftedRm"),
+     (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
+                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", "$Rdn, $imm"),
+     (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p,
+                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", "$Rdn, $Rm"),
+     (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
+                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", "$Rdn, $ShiftedRm"),
+     (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
+                                    cc_out:$s)>;
 }
 
 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
 //  rotate operation that produces a value.
 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
    // 5-bit imm
    def ri : T2sTwoRegShiftImm<
                  (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,

 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
 
 def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm),
             (t2SUBSri $Rn, t2_so_imm:$imm)>;
 def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>;
 def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
             (t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>;
 
-let hasPostISelHook = 1 in {
-defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;
-defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;
-}
+defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1, 1>;
+defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc", ARMsube, 0, 1>;
 
 def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm",
                  (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
+def : t2InstSubst<"adc${s}${p} $rdn, $imm",
+                 (t2SBCri rGPR:$rdn, rGPR:$rdn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm",
                  (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
+def : t2InstSubst<"sbc${s}${p} $rdn, $imm",
+                 (t2ADCri rGPR:$rdn, rGPR:$rdn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
 
 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
                  (t2SUBri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
                  (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
                  (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
 def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",

 //
 
 // Aliases for ADC without the ".w" optional width specifier.
 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
                   (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
+def : t2InstAlias<"adc${s}${p} $Rdn, $Rm",
+                  (t2ADCrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"adc${s}${p} $Rdn, $ShiftedRm",
+                  (t2ADCrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm,
+                           pred:$p, cc_out:$s)>;
 
 // Aliases for SBC without the ".w" optional width specifier.
 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
                   (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
 

llvm/test/MC/ARM/basic-thumb2-instructions.s

@------------------------------------------------------------------------------
         adcs r0, r1, #0
         adc r1, r2, #255
         adc r3, r7, #0x00550055
         adc r8, r12, #0xaa00aa00
         adc r9, r7, #0xa5a5a5a5
         adc r5, r3, #0x87000000
         adc r4, r2, #0x7f800000
         adc r4, r2, #0x00000680
+        adc r0, #1
+        adc r1, #0x7f800000
 
 @ CHECK: adc  r0, r1, #4              @ encoding: [0x41,0xf1,0x04,0x00]
 @ CHECK: adcs  r0, r1, #0              @ encoding: [0x51,0xf1,0x00,0x00]
 @ CHECK: adc  r1, r2, #255            @ encoding: [0x42,0xf1,0xff,0x01]
 @ CHECK: adc  r3, r7, #5570645        @ encoding: [0x47,0xf1,0x55,0x13]
 @ CHECK: adc  r8, r12, #2852170240    @ encoding: [0x4c,0xf1,0xaa,0x28]
 @ CHECK: adc  r9, r7, #2779096485     @ encoding: [0x47,0xf1,0xa5,0x39]
 @ CHECK: adc  r5, r3, #2264924160     @ encoding: [0x43,0xf1,0x07,0x45]
 @ CHECK: adc  r4, r2, #2139095040     @ encoding: [0x42,0xf1,0xff,0x44]
 @ CHECK: adc  r4, r2, #1664           @ encoding: [0x42,0xf5,0xd0,0x64]
+@ CHECK: adc  r0, r0, #1              @ encoding: [0x40,0xf1,0x01,0x00]
+@ CHECK: adc  r1, r1, #2139095040     @ encoding: [0x41,0xf1,0xff,0x41]
 
 @------------------------------------------------------------------------------
 @ ADC (register)
 @------------------------------------------------------------------------------
         adc r4, r5, r6
         adcs r4, r5, r6
         adc.w r9, r1, r3
         adcs.w r9, r1, r3
         adc r0, r1, r3, ror #4
         adcs  r0, r1, r3, lsl #7
         adc.w r0, r1, r3, lsr #31
         adcs.w  r0, r1, r3, asr #32
+        adc r4, r5
+        adc.w r9, r1
+        adc r0, r1, ror #4
+        adc.w r0, r1, lsr #31
 
 @ CHECK: adc.w  r4, r5, r6              @ encoding: [0x45,0xeb,0x06,0x04]
 @ CHECK: adcs.w  r4, r5, r6              @ encoding: [0x55,0xeb,0x06,0x04]
 @ CHECK: adc.w  r9, r1, r3              @ encoding: [0x41,0xeb,0x03,0x09]
 @ CHECK: adcs.w  r9, r1, r3              @ encoding: [0x51,0xeb,0x03,0x09]
 @ CHECK: adc.w  r0, r1, r3, ror #4      @ encoding: [0x41,0xeb,0x33,0x10]
 @ CHECK: adcs.w  r0, r1, r3, lsl #7      @ encoding: [0x51,0xeb,0xc3,0x10]
 @ CHECK: adc.w  r0, r1, r3, lsr #31     @ encoding: [0x41,0xeb,0xd3,0x70]
 @ CHECK: adcs.w  r0, r1, r3, asr #32     @ encoding: [0x51,0xeb,0x23,0x00]
+@ CHECK: adc.w  r4, r4, r5              @ encoding: [0x44,0xeb,0x05,0x04]
+@ CHECK: adc.w  r9, r9, r1              @ encoding: [0x49,0xeb,0x01,0x09]
+@ CHECK: adc.w  r0, r0, r1, ror #4      @ encoding: [0x40,0xeb,0x31,0x10]
+@ CHECK: adc.w  r0, r0, r1, lsr #31     @ encoding: [0x40,0xeb,0xd1,0x70]
 
 
 @------------------------------------------------------------------------------
 @ ADD (immediate)
 @------------------------------------------------------------------------------
         itet eq
         addeq r1, r2, #4
         addwne r5, r3, #1023

llvm/test/MC/Disassembler/ARM/thumb2.txt

 # RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s
 
 #------------------------------------------------------------------------------
 # ADC (immediate)
 #------------------------------------------------------------------------------
 # CHECK: adc r0, r1, #4
 # CHECK: adcs r0, r1, #0
 # CHECK: adc r1, r2, #255
 # CHECK: adc r3, r7, #5570645
 # CHECK: adc r8, r12, #2852170240
 # CHECK: adc r9, r7, #2779096485
 # CHECK: adc r5, r3, #2264924160
 # CHECK: adc r4, r2, #2139095040
 # CHECK: adc r4, r2, #1664
+# CHECK: adc  r0, r0, #1
+# CHECK: adc  r1, r1, #2139095040
 
 0x41 0xf1 0x04 0x00
 0x51 0xf1 0x00 0x00
 0x42 0xf1 0xff 0x01
 0x47 0xf1 0x55 0x13
 0x4c 0xf1 0xaa 0x28
 0x47 0xf1 0xa5 0x39
 0x43 0xf1 0x07 0x45
 0x42 0xf1 0xff 0x44
 0x42 0xf5 0xd0 0x64
+0x40 0xf1 0x01 0x00
+0x41 0xf1 0xff 0x41
 
 #------------------------------------------------------------------------------
 # ADC (register)
 #------------------------------------------------------------------------------
 # CHECK: adc.w r4, r5, r6
 # CHECK: adcs.w r4, r5, r6
 # CHECK: adc.w r9, r1, r3
 # CHECK: adcs.w r9, r1, r3
 # CHECK: adc.w r0, r1, r3, ror #4
 # CHECK: adcs.w  r0, r1, r3, lsl #7
 # CHECK: adc.w r0, r1, r3, lsr #31
 # CHECK: adcs.w  r0, r1, r3, asr #32
+# CHECK: adc.w  r4, r4, r5
+# CHECK: adc.w  r9, r9, r1
+# CHECK: adc.w  r0, r0, r1, ror #4
+# CHECK: adc.w  r0, r0, r1, lsr #31
 
 0x45 0xeb 0x06 0x04
 0x55 0xeb 0x06 0x04
 0x41 0xeb 0x03 0x09
 0x51 0xeb 0x03 0x09
 0x41 0xeb 0x33 0x10
 0x51 0xeb 0xc3 0x10
 0x41 0xeb 0xd3 0x70
 0x51 0xeb 0x23 0x00
+0x44 0xeb 0x05 0x04
+0x49 0xeb 0x01 0x09
+0x40 0xeb 0x31 0x10
+0x40 0xeb 0xd1 0x70
 
 
 #------------------------------------------------------------------------------
 # ADD (immediate)
 #------------------------------------------------------------------------------
 # CHECK: itet eq
 # CHECK: addeq r1, r2, #4
 # CHECK: addwne r5, r3, #1023