Resolve a FIXME in MachineCopyPropagation by allowig propagation to subregister uses.

[arsenm]

llvm/lib/CodeGen/MachineCopyPropagation.cpp

605

This should bail as before rather than assert, the result class might not support the index

[resistor]

llvm/lib/CodeGen/MachineCopyPropagation.cpp

605

Can you explain how that scenario could arise? I'm unable to picture it, and I didn't hit any cases of it in the test suite.

[barannikov88]

llvm/lib/CodeGen/MachineCopyPropagation.cpp

598–602

What does "subregister of the COPY" mean? Is it subregister of the source or the destination operand?

601

MCP ever works with physical registers.

605

I suppose it could be in the case of cross-class copy:

$a = COPY $b
use $sub_a

Here, $sub_a is a sub-register of $a and its index is sub_a_idx.
$b may not have sub_a_idx subregister index if $a and $b are in different register classes.

639–643

Should be in the else branch of the if below.

[arsenm]

llvm/lib/CodeGen/MachineCopyPropagation.cpp

605

I don't know, but the API says it can fail and you can skip it as before.

605

I was also thinking of the cross bank case (but the API says it can fail, so it should be handled, or the unreachable needs to be moved into getSubRegIndex). I'd kind of expect the rest of allocation to try to avoid the cases where this would happen, but I assume a handcrafted MIR test could break this

[resistor]

Update for review feedback.

[resistor]

Ping

[barannikov88]

Missclick, LGTM

llvm/lib/CodeGen/MachineCopyPropagation.cpp

if (!Copy)
       continue;
 
     std::optional<DestSourcePair> CopyOperands =
         isCopyInstr(*Copy, *TII, UseCopyInstr);
     Register CopyDstReg = CopyOperands->Destination->getReg();
     const MachineOperand &CopySrc = *CopyOperands->Source;
     Register CopySrcReg = CopySrc.getReg();
 
-    // FIXME: Don't handle partial uses of wider COPYs yet.
+    // When the use is a subregister of the COPY destination,
+    // record the subreg index.
+    unsigned SubregIdx = 0;
+
+    // This can only occur when we are dealing with physical registers.
     if (MOUse.getReg() != CopyDstReg) {
-      LLVM_DEBUG(
-          dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n  "
-                 << MI);
+      SubregIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg());
+      if (!SubregIdx)
         continue;
     }
 
     // Don't forward COPYs of reserved regs unless they are constant.
     if (MRI->isReserved(CopySrcReg) && !MRI->isConstantPhysReg(CopySrcReg))
       continue;
 
     if (!isForwardableRegClassCopy(*Copy, MI, OpIdx))
       continue;
if (!DebugCounter::shouldExecute(FwdCounter)) {
                         << MI);
       continue;
     }
 
     LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
                       << "\n     with " << printReg(CopySrcReg, TRI)
                       << "\n     in " << MI << "     from " << *Copy);
 
+    if (SubregIdx)
+      MOUse.setReg(TRI->getSubReg(CopySrcReg, SubregIdx));
+    else
       MOUse.setReg(CopySrcReg);
+
     if (!CopySrc.isRenamable())
       MOUse.setIsRenamable(false);
     MOUse.setIsUndef(CopySrc.isUndef());
 
     LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
 
     // Clear kill markers that may have been invalidated.
     for (MachineInstr &KMI :

llvm/test/CodeGen/Thumb2/mve-vst3.ll

 ; CHECK-NEXT:    vmov.32 q2[1], r3
 ; CHECK-NEXT:    vstrw.32 q6, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q6, [r0, #16]
 ; CHECK-NEXT:    vstrw.32 q2, [r1, #16]
 ; CHECK-NEXT:    vmov.f32 s20, s22
 ; CHECK-NEXT:    vmov.f32 s22, s3
 ; CHECK-NEXT:    vstrw.32 q7, [sp, #48] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s9, s0
-; CHECK-NEXT:    vmov.f32 s8, s4
-; CHECK-NEXT:    vmov.f32 s11, s5
 ; CHECK-NEXT:    vmov.f32 s0, s30
-; CHECK-NEXT:    vstrw.32 q2, [sp, #128] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s1, s15
-; CHECK-NEXT:    vldrw.u32 q2, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s2, s19
 ; CHECK-NEXT:    vmov.f32 s3, s31
 ; CHECK-NEXT:    vstrw.32 q0, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT:    vmov.f32 s8, s4
+; CHECK-NEXT:    vmov.f32 s11, s5
 ; CHECK-NEXT:    vmov.f32 s0, s17
+; CHECK-NEXT:    vstrw.32 q2, [sp, #128] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s2, s14
+; CHECK-NEXT:    vldrw.u32 q2, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s3, s18
 ; CHECK-NEXT:    vmov.f32 s21, s7
+; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q0, [sp, #96] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #32]
-; CHECK-NEXT:    vmov.f32 s22, s11
-; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f64 d0, d4
-; CHECK-NEXT:    vmov.f32 s19, s10
-; CHECK-NEXT:    vldrw.u32 q2, [sp, #80] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s21, s7
-; CHECK-NEXT:    vmov.f64 d14, d4
 ; CHECK-NEXT:    vmov.f32 s20, s2
 ; CHECK-NEXT:    vmov.f32 s23, s3
+; CHECK-NEXT:    vldrw.u32 q0, [sp, #64] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s22, s11
 ; CHECK-NEXT:    vstrw.32 q5, [sp, #32] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s21, s16
 ; CHECK-NEXT:    vmov.f32 s23, s13
-; CHECK-NEXT:    vmov.f32 s16, s1
-; CHECK-NEXT:    vmov.f32 s13, s0
-; CHECK-NEXT:    vldrw.u32 q0, [sp, #64] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s16, s9
+; CHECK-NEXT:    vmov.f32 s19, s10
+; CHECK-NEXT:    vmov.f32 s13, s8
+; CHECK-NEXT:    vldrw.u32 q2, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s20, s12
+; CHECK-NEXT:    vmov.f64 d14, d4
 ; CHECK-NEXT:    vmov r0, r3, d14
 ; CHECK-NEXT:    vldrw.u32 q7, [sp, #48] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s7, s11
 ; CHECK-NEXT:    vmov.f32 s8, s24
 ; CHECK-NEXT:    vmov.f32 s9, s0
 ; CHECK-NEXT:    vmov.f32 s11, s25
-; CHECK-NEXT:    vmov.f32 s20, s12
 ; CHECK-NEXT:    vmov.f32 s12, s4
 ; CHECK-NEXT:    vmov.f32 s4, s10
 ; CHECK-NEXT:    vmov.32 q2[2], r0
 ; CHECK-NEXT:    vmov r0, lr, d14
 ; CHECK-NEXT:    vldrw.u32 q7, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s18, s6
 ; CHECK-NEXT:    vmov.32 q5[2], r0
 ; CHECK-NEXT:    vmov.f64 d12, d14