[P10] Fix the implementation for BRH

[lei]

Summary

Fixes the patterns for the brh instruction to include a clrldi when emitted.

[maryammo]

LGTM

[amyk]

LGTM as well.

llvm/lib/Target/PowerPC/PPCInstrP10.td

def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                                v2i64:$vB))]>;
   def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vdiveud $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA,
                                v2i64:$vB))]>;
   def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
                                     "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
   def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RS),
-                     "brh $RA, $RS", IIC_IntRotate,
-                     [(set i32:$RA, (srl (bswap i32:$RS), (i32 16)))]>;
+                     "brh $RA, $RS", IIC_IntRotate, []>;
   def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RS),
                      "brw $RA, $RS", IIC_IntRotate,
                      [(set i32:$RA, (bswap i32:$RS))]>;
   let isCodeGenOnly = 1 in {
     def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RS),
                         "brh $RA, $RS", IIC_IntRotate, []>;
     def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RS),
                         "brw $RA, $RS", IIC_IntRotate, []>;
let Predicates = [IsISA3_1] in {
   def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
             (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
             (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
             (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
-
+  def : Pat<(srl (bswap i32:$RS), (i32 16)),
+            (RLDICL_32 (BRH $RS), 0, 48)>;
+  def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))),
+            (RLDICL_32_64 (BRH $RS), 0, 48)>;
   def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),
              (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),
              (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)),
              (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)),
              (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;

llvm/test/CodeGen/PowerPC/p10-bswap.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
 
 ; Check that the brh/brw/brd instructions are generated for the bswap
 ; intrinsic for register operand on P10 and that the lhbrx/lwbrx/ldbrw
 ; instructions are generated for memory operand.
 
 declare i16 @llvm.bswap.i16(i16)
 
 define zeroext i16 @test_nomem16(i16 zeroext %a) {
 ; CHECK-LABEL: test_nomem16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    brh r3, r3
-; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   ret i16 %0
 }
 
 declare i32 @llvm.bswap.i32(i32)
 

 }
 
 ; Check that brh and clrldi are produced from a call to @llvm.bswap.i32
 ; followed by a right shift of 16 (and a zero-extend at the end of the DAG).
 define zeroext i32 @test_bswap_shift16(i32 zeroext %a) {
 ; CHECK-LABEL: test_bswap_shift16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    brh r3, r3
-; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.bswap.i32(i32 %a)
   %shr = lshr i32 %0, 16
   ret i32 %shr
 }
 
 ; Check that brh are produced from a call to @llvm.bswap.i32
 ; followed by a right shift of 16.
 declare i64 @call_1()
 define void @test_bswap_shift16_2() {
 ; CHECK-LABEL: test_bswap_shift16_2:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    bl call_1@notoc
 ; CHECK-NEXT:    brh r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 0, 48
 ; CHECK-NEXT:    sth r3, 0(r3)
 bb:
   switch i32 undef, label %bb1 [
     i32 78, label %bb2
   ]
 
 bb1:
   unreachable