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Differential D14114

[mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions
ClosedPublic

Authored by zbuljan on Oct 27 2015, 6:22 AM.

Details

Reviewers
dsanders
zoran.jovanovic
hvarga
Commits
rL253329: [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W…
Summary

The patch implements microMIPSDSP instructions: SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 38535.Oct 27 2015, 6:22 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptOct 27 2015, 6:22 AM
dsanders accepted this revision.Nov 14 2015, 5:55 AM
dsanders edited edge metadata.

LGTM with a small test change.

test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
18–25

The DSPr1 tests should also be present. Likewise for the assembler tests.

See my comment on D14058 for more info.

This revision is now accepted and ready to land.Nov 14 2015, 5:55 AM
Closed by commit rL253329: [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W… (authored by zbuljan). · Explain WhyNov 17 2015, 2:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
26 lines
26 lines
test/
MC/
Disassembler/
Mips/
micromips-dsp/
5 lines
micromips-dspr2/
8 lines
Mips/
micromips-dsp/
5 lines
micromips-dspr2/
8 lines

Diff 38535

lib/Target/Mips/MicroMipsDSPInstrInfo.td

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class SHLL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shll.qb", 0b0100001>; class SHLL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shll.qb", 0b0100001>;
class SHLLV_PH_MM_ENC : POOL32A_3R_FMT<"shllv.ph", 0b00000001110>; class SHLLV_PH_MM_ENC : POOL32A_3R_FMT<"shllv.ph", 0b00000001110>;
class SHLLV_S_PH_MM_ENC : POOL32A_3R_FMT<"shllv_s.ph", 0b10000001110>; class SHLLV_S_PH_MM_ENC : POOL32A_3R_FMT<"shllv_s.ph", 0b10000001110>;
class SHLLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shllv.qb", 0b1110010101>; class SHLLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shllv.qb", 0b1110010101>;
class SHLLV_S_W_MM_ENC : POOL32A_3RB0_FMT<"shllv_s.w", 0b1111010101>; class SHLLV_S_W_MM_ENC : POOL32A_3RB0_FMT<"shllv_s.w", 0b1111010101>;
class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>; class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>;
class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>; class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>;
class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>; class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>;
class SUBQ_PH_MM_ENC : POOL32A_3R_FMT<"subq.ph", 0b01000001101>;
class SUBQ_S_PH_MM_ENC : POOL32A_3R_FMT<"subq_s.ph", 0b11000001101>;
class SUBQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"subq_s.w", 0b1101000101>;
class SUBQH_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh.ph", 0b01001001101>;
class SUBQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.ph", 0b11001001101>;
class SUBQH_W_MMR2_ENC : POOL32A_3R_FMT<"subqh.w", 0b01010001101>;
class SUBQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.w", 0b11010001101>;
class SUBU_PH_MMR2_ENC : POOL32A_3R_FMT<"subu.ph", 0b01100001101>;
class SUBU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"subu_s.ph", 0b11100001101>;
class SUBU_QB_MM_ENC : POOL32A_3R_FMT<"subu.qb", 0b01011001101>;
class SUBU_S_QB_MM_ENC : POOL32A_3R_FMT<"subu_s.qb", 0b11011001101>;
class SUBUH_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh.qb", 0b01101001101>;
class SUBUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh_r.qb", 0b11101001101>;
// Instruction desc. // Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROD, InstrItinClass itin, RegisterOperand ROD,
RegisterOperand ROS = ROD> { RegisterOperand ROS = ROD> {
dag OutOperandList = (outs ROD:$rt); dag OutOperandList = (outs ROD:$rt);
dag InOperandList = (ins ROS:$rs); dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(opstr, "\t$rt, $rs"); string AsmString = !strconcat(opstr, "\t$rt, $rs");
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def SHLL_PH_MM : DspMMRel, SHLL_PH_MM_ENC, SHLL_PH_MM_DESC; def SHLL_PH_MM : DspMMRel, SHLL_PH_MM_ENC, SHLL_PH_MM_DESC;
def SHLL_S_PH_MM : DspMMRel, SHLL_S_PH_MM_ENC, SHLL_S_PH_MM_DESC; def SHLL_S_PH_MM : DspMMRel, SHLL_S_PH_MM_ENC, SHLL_S_PH_MM_DESC;
def SHLL_QB_MM : DspMMRel, SHLL_QB_MM_ENC, SHLL_QB_MM_DESC; def SHLL_QB_MM : DspMMRel, SHLL_QB_MM_ENC, SHLL_QB_MM_DESC;
def SHLLV_PH_MM : DspMMRel, SHLLV_PH_MM_ENC, SHLLV_PH_MM_DESC; def SHLLV_PH_MM : DspMMRel, SHLLV_PH_MM_ENC, SHLLV_PH_MM_DESC;
def SHLLV_S_PH_MM : DspMMRel, SHLLV_S_PH_MM_ENC, SHLLV_S_PH_MM_DESC; def SHLLV_S_PH_MM : DspMMRel, SHLLV_S_PH_MM_ENC, SHLLV_S_PH_MM_DESC;
def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC; def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC;
def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC; def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC;
def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC; def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC;
def SUBQ_PH_MM : DspMMRel, SUBQ_PH_MM_ENC, SUBQ_PH_DESC;
def SUBQ_S_PH_MM : DspMMRel, SUBQ_S_PH_MM_ENC, SUBQ_S_PH_DESC;
def SUBQ_S_W_MM : DspMMRel, SUBQ_S_W_MM_ENC, SUBQ_S_W_DESC;
def SUBU_QB_MM : DspMMRel, SUBU_QB_MM_ENC, SUBU_QB_DESC;
def SUBU_S_QB_MM : DspMMRel, SUBU_S_QB_MM_ENC, SUBU_S_QB_DESC;
// microMIPS DSP Rev 2 // microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2; ISA_DSPR2;
def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2; def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2; def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2; def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2; def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2; def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2; def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2;
def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2; def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC, def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
ISA_DSPR2; ISA_DSPR2;
def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC, def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
ISA_DSPR2; ISA_DSPR2;
def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2; def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2; def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2;
def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC, def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
ISA_DSPR2; ISA_DSPR2;
def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2;
def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2;
def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2;
def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2;
def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;

lib/Target/Mips/MipsDSPInstrInfo.td

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// Pseudos. // Pseudos.
def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
NoItinerary>, Uses<[DSPPos]>; NoItinerary>, Uses<[DSPPos]>;
// Instruction defs. // Instruction defs.
// MIPS DSP Rev 1 // MIPS DSP Rev 1
def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC; def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC; def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC; def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC; def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC; def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC; def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
def MODSUB : MODSUB_ENC, MODSUB_DESC; def MODSUB : MODSUB_ENC, MODSUB_DESC;
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC; def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
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def RDDSP : RDDSP_ENC, RDDSP_DESC; def RDDSP : RDDSP_ENC, RDDSP_DESC;
def WRDSP : WRDSP_ENC, WRDSP_DESC; def WRDSP : WRDSP_ENC, WRDSP_DESC;
// MIPS DSP Rev 2 // MIPS DSP Rev 2
let Predicates = [HasDSPR2] in { let Predicates = [HasDSPR2] in {
def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC; def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC; def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC; def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC; def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC; def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC; def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC; def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC; def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC; def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
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test/MC/Disassembler/Mips/micromips-dsp/valid.txt

Show All 22 Lines
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5 0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5
0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5 0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
0x00 0xa4 0x1a 0x0d # CHECK: subq.ph $3, $4, $5
0x00 0xa4 0x1e 0x0d # CHECK: subq_s.ph $3, $4, $5
0x00 0xa4 0x1b 0x45 # CHECK: subq_s.w $3, $4, $5
0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5

test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

Show All 9 Lines
0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5 0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5
0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4 0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4
0x00 0x43 0x00 0xbc # CHECK: dpa.w.ph $ac0, $3, $2 0x00 0x43 0x00 0xbc # CHECK: dpa.w.ph $ac0, $3, $2
0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7 0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7
0x00 0xc5 0x32 0xbc # CHECK: dpaqx_sa.w.ph $ac0, $5, $6 0x00 0xc5 0x32 0xbc # CHECK: dpaqx_sa.w.ph $ac0, $5, $6
0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1 0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1
0x00 0x64 0xa1 0xfc # CHECK: shra.qb $3, $4, 5 0x00 0x64 0xa1 0xfc # CHECK: shra.qb $3, $4, 5
0x00 0x64 0xb1 0xfc # CHECK: shra_r.qb $3, $4, 5 0x00 0x64 0xb1 0xfc # CHECK: shra_r.qb $3, $4, 5
0x00 0xa4 0x1a 0x4d # CHECK: subqh.ph $3, $4, $5
0x00 0xa4 0x1e 0x4d # CHECK: subqh_r.ph $3, $4, $5
0x00 0xa4 0x1a 0x8d # CHECK: subqh.w $3, $4, $5
0x00 0xa4 0x1e 0x8d # CHECK: subqh_r.w $3, $4, $5
0x00 0xa4 0x1b 0x0d # CHECK: subu.ph $3, $4, $5
0x00 0xa4 0x1f 0x0d # CHECK: subu_s.ph $3, $4, $5
0x00 0xa4 0x1b 0x4d # CHECK: subuh.qb $3, $4, $5
0x00 0xa4 0x1f 0x4d # CHECK: subuh_r.qb $3, $4, $5
dsandersUnsubmitted
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The DSPr1 tests should also be present. Likewise for the assembler tests.

See my comment on D14058 for more info.

dsanders: The DSPr1 tests should also be present. Likewise for the assembler tests. See my comment on…

test/MC/Mips/micromips-dsp/valid.s

Show All 23 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e] shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e]
shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e] shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e]
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95] shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5] shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5] shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
subq.ph $3, $4, $5 # CHECK: subq.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x0d]
subq_s.ph $3, $4, $5 # CHECK: subq_s.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1e,0x0d]
subq_s.w $3, $4, $5 # CHECK: subq_s.w $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x45]
subu.qb $3, $4, $5 # CHECK: subu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xcd]
subu_s.qb $3, $4, $5 # CHECK: subu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1e,0xcd]

test/MC/Mips/micromips-dspr2/valid.s

Show All 10 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
adduh_r.qb $3, $4, $5 # CHECK: adduh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x4d] adduh_r.qb $3, $4, $5 # CHECK: adduh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x4d]
absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x00,0x64,0x01,0x3c] absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x00,0x64,0x01,0x3c]
dpa.w.ph $ac0, $3, $2 # CHECK: dpa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x00,0xbc] dpa.w.ph $ac0, $3, $2 # CHECK: dpa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x00,0xbc]
dpaqx_s.w.ph $ac3, $12, $7 # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc] dpaqx_s.w.ph $ac3, $12, $7 # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc]
dpaqx_sa.w.ph $ac0, $5, $6 # CHECK: dpaqx_sa.w.ph $ac0, $5, $6 # encoding: [0x00,0xc5,0x32,0xbc] dpaqx_sa.w.ph $ac0, $5, $6 # CHECK: dpaqx_sa.w.ph $ac0, $5, $6 # encoding: [0x00,0xc5,0x32,0xbc]
dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc] dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc]
shra.qb $3, $4, 5 # CHECK: shra.qb $3, $4, 5 # encoding: [0x00,0x64,0xa1,0xfc] shra.qb $3, $4, 5 # CHECK: shra.qb $3, $4, 5 # encoding: [0x00,0x64,0xa1,0xfc]
shra_r.qb $3, $4, 5 # CHECK: shra_r.qb $3, $4, 5 # encoding: [0x00,0x64,0xb1,0xfc] shra_r.qb $3, $4, 5 # CHECK: shra_r.qb $3, $4, 5 # encoding: [0x00,0x64,0xb1,0xfc]
subqh.ph $3, $4, $5 # CHECK: subqh.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x4d]
subqh_r.ph $3, $4, $5 # CHECK: subqh_r.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1e,0x4d]
subqh.w $3, $4, $5 # CHECK: subqh.w $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x8d]
subqh_r.w $3, $4, $5 # CHECK: subqh_r.w $3, $4, $5 # encoding: [0x00,0xa4,0x1e,0x8d]
subu.ph $3, $4, $5 # CHECK: subu.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x0d]
subu_s.ph $3, $4, $5 # CHECK: subu_s.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1f,0x0d]
subuh.qb $3, $4, $5 # CHECK: subuh.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x4d]
subuh_r.qb $3, $4, $5 # CHECK: subuh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1f,0x4d]