[Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

[gonglingqin]

Summary

Add these intrinsics to keep consistent with GCC [1].

[1]: https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/larchintrin.h#L33

[SixWeining]

clang/lib/Headers/larchintrin.h

17–20

Should be moved into the belowing #if __loongarch_grlen == 64.

[gonglingqin]

clang/lib/Headers/larchintrin.h

17–20

Thanks. I will modify it.

[gonglingqin]

Address @SixWeining's comment.

[SixWeining]

LGTM.

clang/lib/Headers/larchintrin.h

 /*===------------ larchintrin.h - LoongArch intrinsics ---------------------===
  *
  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  * See https://llvm.org/LICENSE.txt for license information.
  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  *
  *===-----------------------------------------------------------------------===
  */
 
 #ifndef _LOONGARCH_BASE_INTRIN_H
 #define _LOONGARCH_BASE_INTRIN_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+typedef struct rdtime {
+  unsigned int value;
+  unsigned int timeid;
+} __rdtime_t;
+
+#if __loongarch_grlen == 64
+typedef struct drdtime {
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;
+
+extern __inline __drdtime_t
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __rdtime_d(void) {
+  __drdtime_t __drdtime;
+  __asm__ volatile(
+      "rdtime.d %[val], %[tid]\n\t"
+      : [val] "=&r"(__drdtime.dvalue), [tid] "=&r"(__drdtime.dtimeid));
+  return __drdtime;
+}
+#endif
+
+extern __inline __rdtime_t
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __rdtimeh_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimeh.w %[val], %[tid]\n\t"
+                   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
+extern __inline __rdtime_t
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __rdtimel_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimel.w %[val], %[tid]\n\t"
+                   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
 #if __loongarch_grlen == 64
 extern __inline int
     __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     __crc_w_b_w(char _1, int _2) {
   return (int)__builtin_loongarch_crc_w_b_w((char)_1, (int)_2);
 }
 
 extern __inline int

clang/test/CodeGen/LoongArch/intrinsic-la32-error.c

 
 unsigned long int iocsrrd_d(unsigned int a) {
   return __builtin_loongarch_iocsrrd_d(a); // expected-error {{this builtin requires target: loongarch64}}
 }
 
 void iocsrwr_d(unsigned long int a, unsigned int b) {
   __builtin_loongarch_iocsrwr_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void rdtime_d() {
+  __rdtime_d(); // expected-error {{call to undeclared function '__rdtime_d'}}
+}

clang/test/CodeGen/LoongArch/intrinsic-la32.c

 // LA32-NEXT:    tail call void @llvm.loongarch.iocsrwr.w(i32 [[A:%.*]], i32 [[B:%.*]])
 // LA32-NEXT:    tail call void @llvm.loongarch.iocsrwr.w(i32 [[A]], i32 [[B]])
 // LA32-NEXT:    ret void
 //
 void iocsrwr_w(unsigned int a, unsigned int b) {
   __iocsrwr_w(a, b);
   __builtin_loongarch_iocsrwr_w(a, b);
 }
+
+// LA32-LABEL: @rdtime(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// LA32-NEXT:    [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// LA32-NEXT:    ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}

clang/test/CodeGen/LoongArch/intrinsic-la64.c

 // CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.d(i64 [[A:%.*]], i32 [[B:%.*]])
 // CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.d(i64 [[A]], i32 [[B]])
 // CHECK-NEXT:    ret void
 //
 void iocsrwr_d(unsigned long int a, unsigned int b) {
   __iocsrwr_d(a, b);
   __builtin_loongarch_iocsrwr_d(a, b);
 }
+
+// CHECK-LABEL: @rdtime_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT:    ret void
+//
+void rdtime_d() {
+  __rdtime_d();
+}
+
+// CHECK-LABEL: @rdtime(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:    ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}