[InstCombine] Fold logic-and/logic-or by distributive laws part2

[bcl5980]

Summary

Follow up https://reviews.llvm.org/D139408, support and/or+select patterns
X && Z || Y && Z --> (X || Y) && Z
https://alive2.llvm.org/ce/z/EMCkBG
https://alive2.llvm.org/ce/z/Q-YRvr
https://alive2.llvm.org/ce/z/SFkVQc
https://alive2.llvm.org/ce/z/S9MCuJ
https://alive2.llvm.org/ce/z/KZ7zzz

(X || Z) && (Y || Z) --> (X && Y) || Z
https://alive2.llvm.org/ce/z/Ggpa8-
https://alive2.llvm.org/ce/z/nhQRLY
https://alive2.llvm.org/ce/z/zpmEnq
https://alive2.llvm.org/ce/z/7omsrf
https://alive2.llvm.org/ce/z/CWBzBp

[bcl5980]

simpilify code

[bcl5980]

Ping.

[spatel]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2777–2778

Can we add some description of the different possibilities?

I know that handling all of the patterns poison-safely is not uniform, but what if we use freeze to make it safe with regular logic ops instead:
https://alive2.llvm.org/ce/z/xb_moG

There is an existing code example for a similar transform below this block of code - search for "MayNeedFreeze".

llvm/test/Transforms/InstCombine/select-factorize.ll

207

I am struggling to see all of the possible patterns, but this should fold:
https://alive2.llvm.org/ce/z/yXjD82

Does handling that case make the code for this patch simpler?
It might be better to split up the changes either way, just so we can be sure that we are not missing anything.

[bcl5980]

update code first to review. Will add detail comments later.

[bcl5980]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2777–2778

So which way are you prefer now? Not uniform code without freeze instruction or use freeze asap to make code easier?

[spatel]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2777–2778

If there are no known regressions, let's go straight to the code with freeze. That should be the ideal form for most of these patterns.

[bcl5980]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2777–2778

I try a lot of ways to add freeze into the code today. But it looks it will make the code more complicate.
Current code already fix all cases without freeze. What freeze can get benefit is convert logical-and to normal and, logical-or to normal or.
So the question becomes which pattern is better freeze + and + or, select + select? Only if the first pattern is better we need to add freeze I think.
I'm sorry I haven't find a elegant way to do it. Can you give me some suggestions for that?

[spatel]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2777–2778

I don't have any good suggestions, so I suppose this is ok.

It might be possible to reduce select in some of these patterns to a real logic (and/or) instruction as a smaller step.

@nikic or @lebedev.ri might have other ideas.

The tests looks complete, so presumably the logic is correct - have you verified that everything passes with Alive2?

[bcl5980]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2777–2778

I add all proofs in the patch description.

[spatel]

We may still want some folds to reduce selects to real logic, but this is an improvement, so LGTM.

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

if (auto *LHS = dyn_cast<FCmpInst>(CondVal))
                                         /*IsSelectLogical*/ true))
           return replaceInstUsesWith(SI, V);
 
     // (A && B) || (C && B) --> (A || C) && B
     if (match(CondVal, m_LogicalAnd(m_Value(A), m_Value(B))) &&
         match(FalseVal, m_LogicalAnd(m_Value(C), m_Value(D))) &&
         (CondVal->hasOneUse() || FalseVal->hasOneUse())) {
       bool CondLogicAnd = isa<SelectInst>(CondVal);
       bool FalseLogicAnd = isa<SelectInst>(FalseVal);
-      if (CondLogicAnd && FalseLogicAnd) {
-        // (A ? B : 0) ? 1 : (A ? D : 0) --> A ? (B ? 1 : D) : 0
-        if (A == C)
-          return SelectInst::Create(A, Builder.CreateSelect(B, One, D), Zero);
-        // (A ? B : 0) ? 1 : (C ? A : 0) --> A ? (B ? 1 : C) : 0
-        if (A == D)
-          return SelectInst::Create(A, Builder.CreateSelect(B, One, C), Zero);
-        // (A ? B : 0) ? 1 : (B ? D : 0) --> B ? (A ? 1 : D) : 0
-        if (B == C)
-          return SelectInst::Create(B, Builder.CreateSelect(A, One, D), Zero);
-        // (A ? B : 0) ? 1 : (C ? B : 0) --> (A ? 1 : C) ? B : 0
-        if (B == D)
-          return SelectInst::Create(Builder.CreateSelect(A, One, C), B, Zero);
-      }
+      auto AndFactorization = [&](Value *Common, Value *InnerCond,
+                                  Value *InnerVal,
+                                  bool SelFirst = false) -> Instruction * {
+        Value *InnerSel = Builder.CreateSelect(InnerCond, One, InnerVal);
+        if (SelFirst)
+          std::swap(Common, InnerSel);
+        if (FalseLogicAnd || (CondLogicAnd && Common == A))
+          return SelectInst::Create(Common, InnerSel, Zero);
+        else
+          return BinaryOperator::CreateAnd(Common, InnerSel);
+      };
+
+        return AndFactorization(A, B, D);
+        return AndFactorization(A, B, C);
+        return AndFactorization(B, A, D);
+        return AndFactorization(B, A, C, CondLogicAnd && FalseLogicAnd);
     }
   }
 
   if (match(FalseVal, m_Zero())) {
     if (impliesPoison(TrueVal, CondVal)) {
       // Change: A = select B, C, false --> A = and B, C
       return BinaryOperator::CreateAnd(CondVal, TrueVal);
     }
 
     if (auto *LHS = dyn_cast<FCmpInst>(CondVal))
       if (auto *RHS = dyn_cast<FCmpInst>(TrueVal))
         if (Value *V = foldLogicOfFCmps(LHS, RHS, /*IsAnd*/ true,
                                         /*IsSelectLogical*/ true))
           return replaceInstUsesWith(SI, V);
 
     // (A || B) && (C || B) --> (A && C) || B
     if (match(CondVal, m_LogicalOr(m_Value(A), m_Value(B))) &&
         match(TrueVal, m_LogicalOr(m_Value(C), m_Value(D))) &&
         (CondVal->hasOneUse() || TrueVal->hasOneUse())) {
       bool CondLogicOr = isa<SelectInst>(CondVal);
       bool TrueLogicOr = isa<SelectInst>(TrueVal);
-      if (CondLogicOr && TrueLogicOr) {
-        // (A ? 1 : B) ? (A ? 1 : D) : 0 --> A ? 1 : (B ? D : 0)
-        if (A == C)
-          return SelectInst::Create(A, One, Builder.CreateSelect(B, D, Zero));
-        // (A ? 1 : B) ? (C ? 1 : A) : 0 --> A ? 1 : (B ? C : 0)
-        if (A == D)
-          return SelectInst::Create(A, One, Builder.CreateSelect(B, C, Zero));
-        // (A ? 1 : B) ? (B ? 1 : D) : 0 --> B ? 1 : (A ? D : 0)
-        if (B == C)
-          return SelectInst::Create(B, One, Builder.CreateSelect(A, D, Zero));
-        // (A ? 1 : B) ? (C ? 1 : B) : 0 --> (A ? C : 0) ? 1 : B
-        if (B == D)
-          return SelectInst::Create(Builder.CreateSelect(A, C, Zero), One, B);
-      }
+      auto OrFactorization = [&](Value *Common, Value *InnerCond,
+                                 Value *InnerVal,
+                                 bool SelFirst = false) -> Instruction * {
+        Value *InnerSel = Builder.CreateSelect(InnerCond, InnerVal, Zero);
+        if (SelFirst)
+          std::swap(Common, InnerSel);
+        if (TrueLogicOr || (CondLogicOr && Common == A))
+          return SelectInst::Create(Common, One, InnerSel);
+        else
+          return BinaryOperator::CreateOr(Common, InnerSel);
+      };
+
+        return OrFactorization(A, B, D);
+        return OrFactorization(A, B, C);
+        return OrFactorization(B, A, D);
+        return OrFactorization(B, A, C, CondLogicOr && TrueLogicOr);
     }
   }
 
   // We match the "full" 0 or 1 constant here to avoid a potential infinite
   // loop with vectors that may have undefined/poison elements.
   // select a, false, b -> select !a, b, false
   if (match(TrueVal, m_Specific(Zero))) {
     Value *NotCond = Builder.CreateNot(CondVal, "not." + CondVal->getName());

llvm/test/Transforms/InstCombine/select-factorize.ll

;
   %or = select i1 %ac, i1 true, i1 %bc
   call void @use(i1 %ac)
   call void @use(i1 %bc)
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_1(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_1(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %c, %a
   %bc = select i1 %c, i1 %b, i1 false
   %or = select i1 %ac, i1 true, i1 %bc
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_2(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_2(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %c, %a
   %bc = select i1 %b, i1 %c, i1 false
   %or = select i1 %ac, i1 true, i1 %bc
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_3(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_3(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %a, %c
   %bc = select i1 %c, i1 %b, i1 false
   %or = select i1 %ac, i1 true, i1 %bc
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_4(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_4(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %a, %c
   %bc = select i1 %b, i1 %c, i1 false
   %or = select i1 %ac, i1 true, i1 %bc
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_5(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_5(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 true, i1 [[AC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[A:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %c, %a
   %bc = select i1 %c, i1 %b, i1 false
   %or = select i1 %bc, i1 true, i1 %ac
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_6(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_6(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 true, i1 [[AC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[A:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = and i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %c, %a
   %bc = select i1 %b, i1 %c, i1 false
   %or = select i1 %bc, i1 true, i1 %ac
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_7(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_7(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 true, i1 [[AC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[A:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %a, %c
   %bc = select i1 %c, i1 %b, i1 false
   %or = select i1 %bc, i1 true, i1 %ac
   ret i1 %or
 }
 
 define i1 @and_logic_and_logic_or_8(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_8(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 true, i1 [[AC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[A:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = and i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %a, %c
   %bc = select i1 %b, i1 %c, i1 false
   %or = select i1 %bc, i1 true, i1 %ac
   ret i1 %or
 }
 
 define <3 x i1> @and_logic_and_logic_or_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_vector(
-; CHECK-NEXT:    [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[TMP1]], <3 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = and <3 x i1> %c, %a
   %bc = select <3 x i1> %c, <3 x i1> %b, <3 x i1> <i1 false, i1 false, i1 false>
   %or = select <3 x i1> %ac, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> %bc
   ret <3 x i1> %or
 }
 
 define <3 x i1> @and_logic_and_logic_or_vector_poison1(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_vector_poison1(
 ; CHECK-NEXT:    [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
 ; CHECK-NEXT:    [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> <i1 false, i1 poison, i1 false>
 ; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = and <3 x i1> %c, %a
   %bc = select <3 x i1> %c, <3 x i1> %b, <3 x i1> <i1 false, i1 poison, i1 false>
   %or = select <3 x i1> %ac, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> %bc
   ret <3 x i1> %or
 }
 
 define <3 x i1> @and_logic_and_logic_or_vector_poison2(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @and_logic_and_logic_or_vector_poison2(
-; CHECK-NEXT:    [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 poison, i1 true, i1 true>, <3 x i1> [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[TMP1]], <3 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = and <3 x i1> %c, %a
   %bc = select <3 x i1> %c, <3 x i1> %b, <3 x i1> <i1 false, i1 false, i1 false>
   %or = select <3 x i1> %ac, <3 x i1> <i1 poison, i1 true, i1 true>, <3 x i1> %bc
   ret <3 x i1> %or
 }
 
;
   %or = select i1 %bc, i1 true, i1 %ac
   call void @use(i1 %ac)
   call void @use(i1 %bc)
   ret i1 %or
 }
 
 define i1 @and_and_logic_or_1(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_and_logic_or_1(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = and i1 [[C]], [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = and i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %c, %a
   %bc = and i1 %c, %b
   %or = select i1 %ac, i1 true, i1 %bc
   ret i1 %or
 }
 
 define i1 @and_and_logic_or_2(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @and_and_logic_or_2(
-; CHECK-NEXT:    [[AC:%.*]] = and i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = and i1 [[C]], [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 true, i1 [[AC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[A:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = and i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = and i1 %a, %c
   %bc = and i1 %c, %b
   %or = select i1 %bc, i1 true, i1 %ac
   ret i1 %or
 }
 
 define <3 x i1>  @and_and_logic_or_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @and_and_logic_or_vector(
-; CHECK-NEXT:    [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = and <3 x i1> [[C]], [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = and <3 x i1> [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = and <3 x i1> %c, %a
   %bc = and <3 x i1> %c, %b
   %or = select <3 x i1> %ac, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1>  %bc
   ret <3 x i1> %or
 }
 
 define <3 x i1>  @and_and_logic_or_vector_poison(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @and_and_logic_or_vector_poison(
-; CHECK-NEXT:    [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = and <3 x i1> [[C]], [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> [[BC]]
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = and <3 x i1> [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = and <3 x i1> %c, %a
   %bc = and <3 x i1> %c, %b
   %or = select <3 x i1> %ac, <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> %bc
   ret <3 x i1> %or
 }
 
;
   %or = select i1 %bc, i1 %ac, i1 false
   call void @use(i1 %ac)
   call void @use(i1 %bc)
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_1(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_1(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 true, i1 [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 [[BC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[TMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %c, %a
   %bc = select i1 %c, i1 true, i1 %b
   %or = select i1 %ac, i1 %bc, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_2(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_2(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 [[BC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[TMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %c, %a
   %bc = select i1 %b, i1 true, i1 %c
   %or = select i1 %ac, i1 %bc, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_3(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_3(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 true, i1 [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 [[AC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[TMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %c, %a
   %bc = select i1 %c, i1 true, i1 %b
   %or = select i1 %bc, i1 %ac, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_4(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_4(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 [[AC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %c, %a
   %bc = select i1 %b, i1 true, i1 %c
   %or = select i1 %bc, i1 %ac, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_5(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_5(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 true, i1 [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 [[BC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[TMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %a, %c
   %bc = select i1 %c, i1 true, i1 %b
   %or = select i1 %ac, i1 %bc, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_6(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_6(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 [[BC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[TMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %a, %c
   %bc = select i1 %b, i1 true, i1 %c
   %or = select i1 %ac, i1 %bc, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_7(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_7(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[C]], i1 true, i1 [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 [[AC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[TMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %a, %c
   %bc = select i1 %c, i1 true, i1 %b
   %or = select i1 %bc, i1 %ac, i1 false
   ret i1 %or
 }
 
 define i1 @or_logic_or_logic_and_8(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_8(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[A:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select i1 [[B:%.*]], i1 true, i1 [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 [[AC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %a, %c
   %bc = select i1 %b, i1 true, i1 %c
   %or = select i1 %bc, i1 %ac, i1 false
   ret i1 %or
 }
 
 define <3 x i1> @or_logic_or_logic_and_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_vector(
-; CHECK-NEXT:    [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
+; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[TMP1]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = or <3 x i1> %c, %a
   %bc = select <3 x i1> %c, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> %b
   %or = select <3 x i1> %ac, <3 x i1> %bc, <3 x i1> <i1 false, i1 false, i1 false>
   ret <3 x i1> %or
 }
 
 define <3 x i1> @or_logic_or_logic_and_vector_poison1(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_vector_poison1(
 ; CHECK-NEXT:    [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
 ; CHECK-NEXT:    [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> [[B:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = or <3 x i1> %c, %a
   %bc = select <3 x i1> %c, <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> %b
   %or = select <3 x i1> %ac, <3 x i1> %bc, <3 x i1> <i1 false, i1 false, i1 false>
   ret <3 x i1> %or
 }
 
 define <3 x i1> @or_logic_or_logic_and_vector_poison2(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @or_logic_or_logic_and_vector_poison2(
-; CHECK-NEXT:    [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> <i1 false, i1 false, i1 poison>
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
+; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[TMP1]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = or <3 x i1> %c, %a
   %bc = select <3 x i1> %c, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> %b
   %or = select <3 x i1> %ac, <3 x i1> %bc, <3 x i1> <i1 false, i1 false, i1 poison>
   ret <3 x i1> %or
 }
 
;
   %or = select i1 %bc, i1 %ac, i1 false
   call void @use(i1 %ac)
   call void @use(i1 %bc)
   ret i1 %or
 }
 
 define i1 @or_or_logic_and_1(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_or_logic_and_1(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = or i1 [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AC]], i1 [[BC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %c, %a
   %bc = or i1 %b, %c
   %or = select i1 %ac, i1 %bc, i1 false
   ret i1 %or
 }
 
 define i1 @or_or_logic_and_2(i1 %c, i1 %a, i1 %b) {
 ; CHECK-LABEL: @or_or_logic_and_2(
-; CHECK-NEXT:    [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = or i1 [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[BC]], i1 [[AC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[B:%.*]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ac = or i1 %c, %a
   %bc = or i1 %b, %c
   %or = select i1 %bc, i1 %ac, i1 false
   ret i1 %or
 }
 
 define <3 x i1> @or_or_logic_and_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @or_or_logic_and_vector(
-; CHECK-NEXT:    [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = or <3 x i1> [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
+; CHECK-NEXT:    [[OR:%.*]] = or <3 x i1> [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = or <3 x i1> %c, %a
   %bc = or <3 x i1> %b, %c
   %or = select <3 x i1> %ac, <3 x i1> %bc, <3 x i1> <i1 false, i1 false, i1 false>
   ret <3 x i1> %or
 }
 
 define <3 x i1> @or_or_logic_and_vector_poison(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
 ; CHECK-LABEL: @or_or_logic_and_vector_poison(
-; CHECK-NEXT:    [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[BC:%.*]] = or <3 x i1> [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> <i1 poison, i1 false, i1 false>
+; CHECK-NEXT:    [[TMP1:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
+; CHECK-NEXT:    [[OR:%.*]] = or <3 x i1> [[TMP1]], [[C:%.*]]
 ; CHECK-NEXT:    ret <3 x i1> [[OR]]
 ;
   %ac = or <3 x i1> %c, %a
   %bc = or <3 x i1> %b, %c
   %or = select <3 x i1> %ac, <3 x i1> %bc, <3 x i1> <i1 poison, i1 false, i1 false>
   ret <3 x i1> %or
 }