AArch64: add CodeGen support for FEAT_XS DSB instructions

[t.p.northover]

Summary

The new variants like dsb ishnxs map naturally to CRm == {16, 20, 24, 28}, extending the existing space of immediates for __builtin_arm_dsb. This adds Clang and backend CodeGen support to emit them when processor support is present, and reasonable diagnostics when it's not.

[tschuett]

The def file is going away:
https://reviews.llvm.org/D139102

[t.p.northover]

Thanks for the warning. Now that's settled down a bit I've updated the patch to the new regime.

[lenary]

I'm not sure I agree with "map naturally", when CRm is a 4-bit field, and both bit 7 and bit 5 are different in the dsb <option> vs dsb <option>nXS instructions.

Are you willing to put this through review for the ACLE? __builtin_arm_dsb is the implementation of __dsb, so I worry that this would make this intrinsic non-portable for clang vs gcc.

clang/include/clang/Basic/DiagnosticSemaKinds.td

def err_first_argument_to_cwsc_pdtor_call : Error<
   "first argument to __builtin_call_with_static_chain must not be a pseudo-destructor call">;
 def err_second_argument_to_cwsc_not_pointer : Error<
   "second argument to __builtin_call_with_static_chain must be of pointer type">;
 
 def err_vector_incorrect_num_initializers : Error<
   "%select{too many|too few}0 elements in vector initialization (expected %1 elements, have %2)">;
 def err_altivec_empty_initializer : Error<"expected initializer">;
 
+def err_arm_invalid_dsb : Error<
+  "DSB argument value %0 is outside valid set {0-15, 16, 20, 24, 28}">;
+def err_arm_invalid_dsb_xs : Error<
+  "DSB argument value %0 requires FEAT_XS support">;
 def err_invalid_neon_type_code : Error<
   "incompatible constant for this __builtin_neon function">;
 def err_argument_invalid_range : Error<
   "argument value %0 is outside the valid range [%1, %2]">;
 def warn_argument_invalid_range : Warning<
   "argument value %0 is outside the valid range [%1, %2]">, DefaultError,
   InGroup<DiagGroup<"argument-outside-range">>;
 def warn_argument_undefined_behaviour : Warning<

clang/lib/Basic/Targets/AArch64.h

class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   bool HasSSBS = false;
   bool HasBTI = false;
   bool HasWFxT = false;
   bool HasJSCVT = false;
   bool HasFCMA = false;
   bool HasNoNeon = false;
   bool HasNoSVE = false;
   bool HasFMV = true;
+  bool HasXS = false;
 
   const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch64::ARMV8A;
 
   std::string ABI;
 
 public:
   AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
 

clang/lib/Basic/Targets/AArch64.cpp

return llvm::StringSwitch<bool>(Feature)
       .Case("sme-i16i64", HasSMEI64)
       .Cases("memtag", "memtag2", HasMTE)
       .Case("sb", HasSB)
       .Case("predres", HasPredRes)
       .Cases("ssbs", "ssbs2", HasSSBS)
       .Case("bti", HasBTI)
       .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
       .Case("wfxt", HasWFxT)
+      .Case("xs", HasXS)
       .Default(false);
 }
 
 void AArch64TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
                                           StringRef Name, bool Enabled) const {
   Features[Name] = Enabled;
   // If the feature is an architecture feature (like v8.2a), add all previous
   // architecture versions and any dependant target features.
if (Feature == "+ccdp") {
       HasCCDP = true;
     }
     if (Feature == "+fptoint")
       HasFRInt3264 = true;
     if (Feature == "+sm4") {
       FPU |= NeonMode;
       HasSM4 = true;
     }
+    if (Feature == "+xs")
+      HasXS = true;
     if (Feature == "+strict-align")
       HasUnaligned = false;
     // All predecessor archs are added but select the latest one for ArchKind.
     if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version)
       ArchInfo = &llvm::AArch64::ARMV8A;
     if (Feature == "+v8.1a" &&
         ArchInfo->Version < llvm::AArch64::ARMV8_1A.Version)
       ArchInfo = &llvm::AArch64::ARMV8_1A;

clang/lib/Sema/SemaChecking.cpp

if (BuiltinID == AArch64::BI__break)
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0xffff);
 
   if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall))
     return true;
 
   if (CheckSVEBuiltinFunctionCall(BuiltinID, TheCall))
     return true;
 
+  if (BuiltinID == AArch64::BI__builtin_arm_dsb) {
+    llvm::APSInt Result;
+    if (SemaBuiltinConstantArg(TheCall, 0, Result))
+      return true;
+    if (Result >= 0 && Result <= 15)
+      return false;
+    else if (Result == 16 || Result == 20 || Result == 24 || Result == 28)
+      return TI.hasFeature("xs")
+                 ? false
+                 : Diag(TheCall->getBeginLoc(), diag::err_arm_invalid_dsb_xs)
+                       << Result.getSExtValue();
+    return Diag(TheCall->getBeginLoc(), diag::err_arm_invalid_dsb)
+           << Result.getSExtValue();
+  }
+
   // For intrinsics which take an immediate value as part of the instruction,
   // range check them here.
   unsigned i = 0, l = 0, u = 0;
   switch (BuiltinID) {
   default: return false;
   case AArch64::BI__builtin_arm_dmb:
-  case AArch64::BI__builtin_arm_dsb:
   case AArch64::BI__builtin_arm_isb: l = 0; u = 15; break;
   case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break;
   }
 
   return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
 }
 
 static bool isValidBPFPreserveFieldInfoArg(Expr *Arg) {

clang/test/Sema/builtins-arm64.c

 // RUN: %clang_cc1 -triple arm64-apple-ios -fsyntax-only -verify %s
 // RUN: %clang_cc1 -triple arm64-apple-ios -DTEST1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +xs -DXS -fsyntax-only -verify %s
 
 #ifdef TEST1
 void __clear_cache(void *start, void *end);
 #endif
 
 void test_clear_cache_chars(char *start, char *end) {
   __clear_cache(start, end);
 }
 
 void test_clear_cache_voids(void *start, void *end) {
   __clear_cache(start, end);
 }
 
 void test_clear_cache_no_args(void) {
   __clear_cache(); // expected-error {{too few arguments to function call}}
 }
 
 void test_memory_barriers(void) {
   __builtin_arm_dmb(16); // expected-error-re {{argument value {{.*}} is outside the valid range}}
-  __builtin_arm_dsb(17); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+  __builtin_arm_dsb(17); // expected-error-re {{DSB argument value {{.*}} is outside valid set}}
   __builtin_arm_isb(18); // expected-error-re {{argument value {{.*}} is outside the valid range}}
+
+#ifdef XS
+  __builtin_arm_dsb(16);
+  __builtin_arm_dsb(20);
+  __builtin_arm_dsb(24);
+  __builtin_arm_dsb(28);
+#else
+  __builtin_arm_dsb(20); // expected-error    {{DSB argument value 20 requires FEAT_XS support}}
+#endif
 }
 
+
 void test_prefetch(void) {
   __builtin_arm_prefetch(0, 2, 0, 0, 0); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   __builtin_arm_prefetch(0, 0, 4, 0, 0); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   __builtin_arm_prefetch(0, 0, 0, 2, 0); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   __builtin_arm_prefetch(0, 0, 0, 0, 2); // expected-error-re {{argument value {{.*}} is outside the valid range}}
 }

llvm/include/llvm/TargetParser/AArch64TargetParser.h

enum ArchExtKind : uint64_t {
   AEK_CSSC =        1ULL << 48, // FEAT_CSSC
   AEK_RCPC3 =       1ULL << 49, // FEAT_LRCPC3
   AEK_THE =         1ULL << 50, // FEAT_THE
   AEK_D128 =        1ULL << 51, // FEAT_D128
   AEK_LSE128 =      1ULL << 52, // FEAT_LSE128
   AEK_SPECRES2 =    1ULL << 53, // FEAT_SPECRES2
   AEK_RASv2 =       1ULL << 54, // FEAT_RASv2
   AEK_ITE =         1ULL << 55, // FEAT_ITE
+  AEK_XS =          1ULL << 56, // FEAT_XS
 };
 // clang-format on
 
 // Represents an extension that can be enabled with -march=<arch>+<extension>.
 // Typically these correspond to Arm Architecture extensions, unlike
 // SubtargetFeature which may represent either an actual extension or some
 // internal LLVM property.
 struct ExtensionInfo {
inline constexpr ExtensionInfo Extensions[] = {
     {"sve2-pmull128", AArch64::AEK_NONE, {}, {}, FEAT_SVE_PMULL128, "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390},
     {"sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3", FEAT_SVE_SHA3, "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410},
     {"sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4", FEAT_SVE_SM4, "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420},
     {"sve2", AArch64::AEK_SVE2, "+sve2", "-sve2", FEAT_SVE2, "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370},
     {"sve2p1", AArch64::AEK_SVE2p1, "+sve2p1", "-sve2p1", FEAT_MAX, "", 0},
     {"the", AArch64::AEK_THE, "+the", "-the", FEAT_MAX, "", 0},
     {"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_MAX, "", 0},
     {"wfxt", AArch64::AEK_NONE, {}, {}, FEAT_WFXT, "+wfxt", 550},
+    {"xs", AArch64::AEK_XS, "+xs", "-xs", FEAT_MAX, "", 0},
     // Special cases
     {"none", AArch64::AEK_NONE, {}, {}, FEAT_MAX, "", ExtensionInfo::MaxFMVPriority},
 };
 // clang-format on
 
 enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' };
 
 // Information about a specific architecture, e.g. V8.1-A

 // clang-format off
 inline constexpr ArchInfo ARMV8A    = { VersionTuple{8, 0}, AProfile, "armv8-a", "+v8a", (AArch64::AEK_FP | AArch64::AEK_SIMD), };
 inline constexpr ArchInfo ARMV8_1A  = { VersionTuple{8, 1}, AProfile, "armv8.1-a", "+v8.1a", (ARMV8A.DefaultExts | AArch64::AEK_CRC | AArch64::AEK_LSE | AArch64::AEK_RDM)};
 inline constexpr ArchInfo ARMV8_2A  = { VersionTuple{8, 2}, AProfile, "armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts | AArch64::AEK_RAS)};
 inline constexpr ArchInfo ARMV8_3A  = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts | AArch64::AEK_RCPC)};
 inline constexpr ArchInfo ARMV8_4A  = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts | AArch64::AEK_DOTPROD)};
 inline constexpr ArchInfo ARMV8_5A  = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
 inline constexpr ArchInfo ARMV8_6A  = { VersionTuple{8, 6}, AProfile, "armv8.6-a", "+v8.6a", (ARMV8_5A.DefaultExts | AArch64::AEK_BF16 | AArch64::AEK_I8MM)};
-inline constexpr ArchInfo ARMV8_7A  = { VersionTuple{8, 7}, AProfile, "armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
+inline constexpr ArchInfo ARMV8_7A  = { VersionTuple{8, 7}, AProfile, "armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts | AArch64::AEK_XS)};
 inline constexpr ArchInfo ARMV8_8A  = { VersionTuple{8, 8}, AProfile, "armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::AEK_MOPS | AArch64::AEK_HBC)};
 inline constexpr ArchInfo ARMV8_9A  = { VersionTuple{8, 9}, AProfile, "armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | AArch64::AEK_SPECRES2 | AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
 inline constexpr ArchInfo ARMV9A    = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (ARMV8_5A.DefaultExts | AArch64::AEK_FP16 | AArch64::AEK_SVE | AArch64::AEK_SVE2)};
 inline constexpr ArchInfo ARMV9_1A  = { VersionTuple{9, 1}, AProfile, "armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | AArch64::AEK_BF16 | AArch64::AEK_I8MM)};
-inline constexpr ArchInfo ARMV9_2A  = { VersionTuple{9, 2}, AProfile, "armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
+inline constexpr ArchInfo ARMV9_2A  = { VersionTuple{9, 2}, AProfile, "armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts | AArch64::AEK_XS)};
 inline constexpr ArchInfo ARMV9_3A  = { VersionTuple{9, 3}, AProfile, "armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | AArch64::AEK_MOPS | AArch64::AEK_HBC)};
 inline constexpr ArchInfo ARMV9_4A  = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts | AArch64::AEK_SPECRES2 | AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
 // For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
 inline constexpr ArchInfo ARMV8R    = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", ((ARMV8_5A.DefaultExts ^ AArch64::AEK_LSE) | AArch64::AEK_SSBS | AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_SB), };
 // clang-format on
 
 // The set of all architectures
 static constexpr std::array<const ArchInfo *, 16> ArchInfos = {

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 
 // timm32_0_255 predicate - True if the 32-bit immediate is in the range [0,255]
 def timm32_0_255 : Operand<i32>, TImmLeaf<i32, [{
   return ((uint32_t)Imm) < 256;
 }]> {
   let ParserMatchClass = Imm0_255Operand;
 }
 
+def DSBnXSXForm : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant((N->getZExtValue() & 0xc) | 3, SDLoc(N), MVT::i32);
+}]>;
+
+def imm32_nXS : ImmLeaf<i32, [{
+  return Imm == 16 || Imm == 20 || Imm == 24 || Imm == 28;
+}], DSBnXSXForm>;
+
 // An arithmetic shifter operand:
 //  {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
 //  {5-0} - imm6
 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
   let PrintMethod = "printShifter";
   let ParserMatchClass = !cast<AsmOperandClass>(
                          "ArithmeticShifterOperand" # width);
 }

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def ISB   : CRmSystemI<barrier_op, 0b110, "isb",
                        [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
 
 def TSB   : CRmSystemI<barrier_op, 0b010, "tsb", []> {
   let CRm        = 0b0010;
   let Inst{12}   = 0;
   let Predicates = [HasTRACEV8_4];
 }
 
-def DSBnXS  : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
+def DSBnXS  : CRmSystemI<barrier_nxs_op, 0b001, "dsb",
+                         [(int_aarch64_dsb (i32 imm32_nXS:$CRm))]> {
   let CRm{1-0}   = 0b11;
   let Inst{9-8}  = 0b10;
   let Predicates = [HasXS];
 }
 
 let Predicates = [HasWFxT] in {
 def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;
 def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;

llvm/test/CodeGen/AArch64/dsb-xs.ll

+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+xs %s -o - | FileCheck %s
+
+define void @test_barriers() {
+; CHECK-LABEL: test_barriers:
+
+; CHECK: dsb oshnxs
+; CHECK: dsb nshnxs
+; CHECK: dsb ishnxs
+; CHECK: dsb synxs
+
+  call void @llvm.aarch64.dsb(i32 16)
+  call void @llvm.aarch64.dsb(i32 20)
+  call void @llvm.aarch64.dsb(i32 24)
+  call void @llvm.aarch64.dsb(i32 28)
+  ret void
+}
+declare void @llvm.aarch64.dsb(i32)

llvm/unittests/TargetParser/TargetParserTest.cpp

std::vector<uint64_t> Extensions = {
       AArch64::AEK_F64MM,   AArch64::AEK_TME,       AArch64::AEK_LS64,
       AArch64::AEK_BRBE,    AArch64::AEK_PAUTH,     AArch64::AEK_FLAGM,
       AArch64::AEK_SME,     AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
       AArch64::AEK_SME2,    AArch64::AEK_HBC,       AArch64::AEK_MOPS,
       AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,    AArch64::AEK_SME2p1,
       AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
       AArch64::AEK_RCPC3,   AArch64::AEK_THE,       AArch64::AEK_D128,
       AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
-      AArch64::AEK_ITE,
+      AArch64::AEK_ITE,     AArch64::AEK_XS,
   };
 
   std::vector<StringRef> Features;
 
   uint64_t ExtVal = 0;
   for (auto Ext : Extensions)
     ExtVal |= Ext;