[AMDGPU][NFC] Isolate KImm operands

[dp]

Summary

KImm operands are (almost) always require special handling.

This patch separates OPERAND_KIMM32 and OPERAND_KIMM16 from other operand kinds. In particular, these operands are excluded from [OPERAND_REG_INLINE_C_FIRST,OPERAND_REG_INLINE_C_LAST] and from [OPERAND_SRC_FIRST,OPERAND_SRC_LAST].
opCanUseInlineConstant, isSISrcOperand and isSISrcInlinableOperand now return false for KImm operands.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
   if (Imm.Mods.Neg) {
     Val ^= FpSignMask;
   }
 
   return Val;
 }
 
 void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
-  if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
-                             Inst.getNumOperands())) {
+  const auto &InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
+  auto OpNum = Inst.getNumOperands();
+  if (AMDGPU::isSISrcOperand(InstDesc, OpNum) ||
+      AMDGPU::isKImmOperand(InstDesc, OpNum)) {
     addLiteralImmOperand(Inst, Imm.Val,
                          ApplyModifiers &
                          isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
   } else {
     assert(!isImmTy(ImmTyNone) || !hasModifiers());
     Inst.addOperand(MCOperand::createImm(Imm.Val));
     setImmKindNone();
   }
 }
 
 void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {
   const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
   auto OpNum = Inst.getNumOperands();
   // Check that this operand accepts literals
-  assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
+  assert(AMDGPU::isSISrcOperand(InstDesc, OpNum) ||
+         AMDGPU::isKImmOperand(InstDesc, OpNum));
 
   if (ApplyModifiers) {
     assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
     const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
     Val = applyInputFPModifiers(Val, Size);
   }
 
   APInt Literal(64, Val);

 // NB: This code is correct only when used to check constant
 // bus limitations because GFX7 support no f16 inline constants.
 // Note that there are no cases when a GFX7 opcode violates
 // constant bus limitations due to the use of an f16 constant.
 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
                                        unsigned OpIdx) const {
   const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
 
-  if (!AMDGPU::isSISrcOperand(Desc, OpIdx) ||
-      AMDGPU::isKImmOperand(Desc, OpIdx)) {
+  if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) {
     return false;
   }
 
   const MCOperand &MO = Inst.getOperand(OpIdx);
 
   int64_t Val = MO.getImm();
   auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);
 
bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
 
   for (int OpIdx : OpIndices) {
     if (OpIdx == -1)
       continue;
 
     const MCOperand &MO = Inst.getOperand(OpIdx);
     if (!MO.isImm() && !MO.isExpr())
       continue;
-    if (!isSISrcOperand(Desc, OpIdx))
+    if (!isSISrcOperand(Desc, OpIdx) && !isKImmOperand(Desc, OpIdx))
       continue;
 
     if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {
       uint32_t Value = static_cast<uint32_t>(MO.getImm());
       if (NumLiterals == 0 || LiteralValue != Value) {
         LiteralValue = Value;
         ++NumLiterals;
       }

llvm/lib/Target/AMDGPU/SIDefines.h

enum OperandType : unsigned {
   OPERAND_REG_INLINE_C_FP16,
   OPERAND_REG_INLINE_C_FP32,
   OPERAND_REG_INLINE_C_FP64,
   OPERAND_REG_INLINE_C_V2INT16,
   OPERAND_REG_INLINE_C_V2FP16,
   OPERAND_REG_INLINE_C_V2INT32,
   OPERAND_REG_INLINE_C_V2FP32,
 
-  /// Operand with 32-bit immediate that uses the constant bus.
-  OPERAND_KIMM32,
-  OPERAND_KIMM16,
-
   /// Operands with an AccVGPR register or inline constant
   OPERAND_REG_INLINE_AC_INT16,
   OPERAND_REG_INLINE_AC_INT32,
   OPERAND_REG_INLINE_AC_FP16,
   OPERAND_REG_INLINE_AC_FP32,
   OPERAND_REG_INLINE_AC_FP64,
   OPERAND_REG_INLINE_AC_V2INT16,
   OPERAND_REG_INLINE_AC_V2FP16,
   OPERAND_REG_INLINE_AC_V2INT32,
   OPERAND_REG_INLINE_AC_V2FP32,
 
+  /// Operand with 32-bit immediate that uses the constant bus.
+  OPERAND_KIMM32,
+  OPERAND_KIMM16,
+
   OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
   OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
 
   OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
   OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,
 
   OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
   OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

bool SIFoldOperands::tryToFoldACImm(
     const MachineOperand &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx,
     SmallVectorImpl<FoldCandidate> &FoldList) const {
   const MCInstrDesc &Desc = UseMI->getDesc();
   const MCOperandInfo *OpInfo = Desc.OpInfo;
   if (!OpInfo || UseOpIdx >= Desc.getNumOperands())
     return false;
 
   uint8_t OpTy = OpInfo[UseOpIdx].OperandType;
-  if ((OpTy < AMDGPU::OPERAND_REG_INLINE_AC_FIRST ||
-       OpTy > AMDGPU::OPERAND_REG_INLINE_AC_LAST) &&
-      (OpTy < AMDGPU::OPERAND_REG_INLINE_C_FIRST ||
-       OpTy > AMDGPU::OPERAND_REG_INLINE_C_LAST))
+  if (OpTy < AMDGPU::OPERAND_REG_INLINE_C_FIRST ||
+      OpTy > AMDGPU::OPERAND_REG_INLINE_C_LAST)
     return false;
 
   if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) &&
       TII->isOperandLegal(*UseMI, UseOpIdx, &OpToFold)) {
     UseMI->getOperand(UseOpIdx).ChangeToImmediate(OpToFold.getImm());
     return true;
   }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

case AMDGPU::OPERAND_REG_INLINE_AC_FP16: {
     return false;
   }
   case AMDGPU::OPERAND_REG_IMM_V2FP16:
   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
     uint32_t Trunc = static_cast<uint32_t>(Imm);
     return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm());
   }
-  case AMDGPU::OPERAND_KIMM32:
-  case AMDGPU::OPERAND_KIMM16:
-    return false;
   default:
     llvm_unreachable("invalid bitwidth");
   }
 }
 
 static bool compareMachineOp(const MachineOperand &Op0,
                              const MachineOperand &Op1) {
   if (Op0.getType() != Op1.getType())
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       if (Op.isReg()) {
         RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
         if (!SGPRsUsed.count(SGPR) &&
             usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
           if (--ConstantBusLimit <= 0)
             return false;
           SGPRsUsed.insert(SGPR);
         }
-      } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 ||
+      } else if (AMDGPU::isKImmOperand(InstDesc, i) ||
                  (AMDGPU::isSISrcOperand(InstDesc, i) &&
                   !isInlineConstant(Op, InstDesc.OpInfo[i]))) {
         if (!LiteralLimit--)
           return false;
         if (--ConstantBusLimit <= 0)
           return false;
       }
     }