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Differential D138152

AMDGPU: Add some baseline tests for llvm.amdgcn.trig.preop folding
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Authored by arsenm on Nov 16 2022, 1:40 PM.

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arsenm created this revision.Nov 16 2022, 1:40 PM
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arsenm requested review of this revision.Nov 16 2022, 1:40 PM
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arsenm added a child revision: D120150: Constant folding of llvm.amdgcn.trig.preop.Nov 16 2022, 1:41 PM
Harbormaster completed remote builds in B198063: Diff 475912.Nov 16 2022, 2:42 PM
arsenm updated this revision to Diff 476234.Nov 17 2022, 2:01 PM

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Harbormaster completed remote builds in B198290: Diff 476234.Nov 17 2022, 2:56 PM
foad accepted this revision.Nov 18 2022, 5:19 AM
This revision is now accepted and ready to land.Nov 18 2022, 5:19 AM
arsenm closed this revision.Nov 18 2022, 9:14 AM

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PathSize
llvm/
test/
Transforms/
InstCombine/
AMDGPU/
201 lines

Diff 475912

llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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; CHECK-NEXT: ret i1 [[VAL]] ; CHECK-NEXT: ret i1 [[VAL]]
; ;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3) %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3)
ret i1 %val ret i1 %val
} }
define i1 @test_class_isnan_f32_strict(float %x) nounwind { define i1 @test_class_isnan_f32_strict(float %x) nounwind {
; CHECK-LABEL: @test_class_isnan_f32_strict( ; CHECK-LABEL: @test_class_isnan_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.amdgcn.class.f32(float [[X:%.*]], i32 3) #[[ATTR15:[0-9]+]] ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.amdgcn.class.f32(float [[X:%.*]], i32 3) #[[ATTR16:[0-9]+]]
; CHECK-NEXT: ret i1 [[VAL]] ; CHECK-NEXT: ret i1 [[VAL]]
; ;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3) strictfp %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3) strictfp
ret i1 %val ret i1 %val
} }
define i1 @test_class_is_p0_n0_f32(float %x) nounwind { define i1 @test_class_is_p0_n0_f32(float %x) nounwind {
; CHECK-LABEL: @test_class_is_p0_n0_f32( ; CHECK-LABEL: @test_class_is_p0_n0_f32(
; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[VAL]] ; CHECK-NEXT: ret i1 [[VAL]]
; ;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96) %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96)
ret i1 %val ret i1 %val
} }
define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind { define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind {
; CHECK-LABEL: @test_class_is_p0_n0_f32_strict( ; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.amdgcn.class.f32(float [[X:%.*]], i32 96) #[[ATTR15]] ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.amdgcn.class.f32(float [[X:%.*]], i32 96) #[[ATTR16]]
; CHECK-NEXT: ret i1 [[VAL]] ; CHECK-NEXT: ret i1 [[VAL]]
; ;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96) strictfp %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96) strictfp
ret i1 %val ret i1 %val
} }
define i1 @test_constant_class_snan_test_snan_f64() nounwind { define i1 @test_constant_class_snan_test_snan_f64() nounwind {
; CHECK-LABEL: @test_constant_class_snan_test_snan_f64( ; CHECK-LABEL: @test_constant_class_snan_test_snan_f64(
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; CHECK-NEXT: ret i64 0 ; CHECK-NEXT: ret i64 0
; ;
%result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32) %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32)
ret i64 %result ret i64 %result
} }
define i64 @icmp_constant_inputs_true() { define i64 @icmp_constant_inputs_true() {
; CHECK-LABEL: @icmp_constant_inputs_true( ; CHECK-LABEL: @icmp_constant_inputs_true(
; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR16:[0-9]+]] ; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR17:[0-9]+]]
; CHECK-NEXT: ret i64 [[RESULT]] ; CHECK-NEXT: ret i64 [[RESULT]]
; ;
%result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34) %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34)
ret i64 %result ret i64 %result
} }
define i64 @icmp_constant_to_rhs_slt(i32 %x) { define i64 @icmp_constant_to_rhs_slt(i32 %x) {
; CHECK-LABEL: @icmp_constant_to_rhs_slt( ; CHECK-LABEL: @icmp_constant_to_rhs_slt(
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; CHECK-NEXT: ret i64 0 ; CHECK-NEXT: ret i64 0
; ;
%result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1) %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1)
ret i64 %result ret i64 %result
} }
define i64 @fcmp_constant_inputs_true() { define i64 @fcmp_constant_inputs_true() {
; CHECK-LABEL: @fcmp_constant_inputs_true( ; CHECK-LABEL: @fcmp_constant_inputs_true(
; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR16]] ; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR17]]
; CHECK-NEXT: ret i64 [[RESULT]] ; CHECK-NEXT: ret i64 [[RESULT]]
; ;
%result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4) %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4)
ret i64 %result ret i64 %result
} }
define i64 @fcmp_constant_to_rhs_olt(float %x) { define i64 @fcmp_constant_to_rhs_olt(float %x) {
; CHECK-LABEL: @fcmp_constant_to_rhs_olt( ; CHECK-LABEL: @fcmp_constant_to_rhs_olt(
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; CHECK-NEXT: ret i64 0 ; CHECK-NEXT: ret i64 0
; ;
%b = call i64 @llvm.amdgcn.ballot.i64(i1 0) %b = call i64 @llvm.amdgcn.ballot.i64(i1 0)
ret i64 %b ret i64 %b
} }
define i64 @ballot_one_64() { define i64 @ballot_one_64() {
; CHECK-LABEL: @ballot_one_64( ; CHECK-LABEL: @ballot_one_64(
; CHECK-NEXT: [[B:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR16]] ; CHECK-NEXT: [[B:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR17]]
; CHECK-NEXT: ret i64 [[B]] ; CHECK-NEXT: ret i64 [[B]]
; ;
%b = call i64 @llvm.amdgcn.ballot.i64(i1 1) %b = call i64 @llvm.amdgcn.ballot.i64(i1 1)
ret i64 %b ret i64 %b
} }
define i32 @ballot_nocombine_32(i1 %i) { define i32 @ballot_nocombine_32(i1 %i) {
; CHECK-LABEL: @ballot_nocombine_32( ; CHECK-LABEL: @ballot_nocombine_32(
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; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
; ;
%b = call i32 @llvm.amdgcn.ballot.i32(i1 0) %b = call i32 @llvm.amdgcn.ballot.i32(i1 0)
ret i32 %b ret i32 %b
} }
define i32 @ballot_one_32() { define i32 @ballot_one_32() {
; CHECK-LABEL: @ballot_one_32( ; CHECK-LABEL: @ballot_one_32(
; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.read_register.i32(metadata [[META1:![0-9]+]]) #[[ATTR16]] ; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.read_register.i32(metadata [[META1:![0-9]+]]) #[[ATTR17]]
; CHECK-NEXT: ret i32 [[B]] ; CHECK-NEXT: ret i32 [[B]]
; ;
%b = call i32 @llvm.amdgcn.ballot.i32(i1 1) %b = call i32 @llvm.amdgcn.ballot.i32(i1 1)
ret i32 %b ret i32 %b
} }
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; llvm.amdgcn.wqm.vote ; llvm.amdgcn.wqm.vote
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define i1 @test_is_private_undef() nounwind { define i1 @test_is_private_undef() nounwind {
; CHECK-LABEL: @test_is_private_undef( ; CHECK-LABEL: @test_is_private_undef(
; CHECK-NEXT: ret i1 undef ; CHECK-NEXT: ret i1 undef
; ;
%val = call i1 @llvm.amdgcn.is.private(ptr undef) %val = call i1 @llvm.amdgcn.is.private(ptr undef)
ret i1 %val ret i1 %val
} }
; --------------------------------------------------------------------
; llvm.amdgcn.trig.preop
; --------------------------------------------------------------------
declare double @llvm.amdgcn.trig.preop.f64(double, i32)
declare float @llvm.amdgcn.trig.preop.f32(float, i32)
define double @trig_preop_constfold_variable_undef_arg(i32 %arg) {
; CHECK-LABEL: @trig_preop_constfold_variable_undef_arg(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double undef, i32 [[ARG:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double undef, i32 %arg)
ret double %val
}
define double @trig_preop_constfold_variable_arg_undef(double %arg) {
; CHECK-LABEL: @trig_preop_constfold_variable_arg_undef(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG:%.*]], i32 undef)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double %arg, i32 undef)
ret double %val
}
define double @trig_preop_constfold_variable_int(i32 %arg) {
; CHECK-LABEL: @trig_preop_constfold_variable_int(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 [[ARG:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 %arg)
ret double %val
}
define double @trig_preop_qnan(i32 %arg) {
; CHECK-LABEL: @trig_preop_qnan(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 [[ARG:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 %arg)
ret double %val
}
define double @trig_preop_snan(i32 %arg) {
; CHECK-LABEL: @trig_preop_snan(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 [[ARG:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 %arg)
ret double %val
}
define double @trig_preop_inf_0() {
; CHECK-LABEL: @trig_preop_inf_0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000000, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000000, i32 0)
ret double %val
}
define double @trig_preop_ninf_0() {
; CHECK-LABEL: @trig_preop_ninf_0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0xFFF0000000000000, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0xFFF0000000000000, i32 0)
ret double %val
}
define double @trig_preop_variable_fp(double %arg) {
; CHECK-LABEL: @trig_preop_variable_fp(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG:%.*]], i32 5)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double %arg, i32 5)
ret double %val
}
define double @trig_preop_variable_args(double %arg0, i32 %arg1) {
; CHECK-LABEL: @trig_preop_variable_args(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG0:%.*]], i32 [[ARG1:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double %arg0, i32 %arg1)
ret double %val
}
define double @trig_preop_constfold() {
; CHECK-LABEL: @trig_preop_constfold(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5)
ret double %val
}
define double @trig_preop_constfold_strictfp() {
; CHECK-LABEL: @trig_preop_constfold_strictfp(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) #[[ATTR16]]
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) strictfp
ret double %val
}
define double @trig_preop_constfold_0.0__0() {
; CHECK-LABEL: @trig_preop_constfold_0.0__0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0.000000e+00, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 0)
ret double %val
}
define double @trig_preop_constfold_0.0__1() {
; CHECK-LABEL: @trig_preop_constfold_0.0__1(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0.000000e+00, i32 1)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 1)
ret double %val
}
define double @trig_preop_constfold_0.0__neg1() {
; CHECK-LABEL: @trig_preop_constfold_0.0__neg1(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0.000000e+00, i32 -1)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 -1)
ret double %val
}
define double @trig_preop_constfold_0.0__9999999() {
; CHECK-LABEL: @trig_preop_constfold_0.0__9999999(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0.000000e+00, i32 9999999)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 9999999)
ret double %val
}
define double @trig_preop_constfold_0.0__neg999999() {
; CHECK-LABEL: @trig_preop_constfold_0.0__neg999999(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0.000000e+00, i32 -999999)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 -999999)
ret double %val
}
define double @trig_preop_constfold_0x0020000000000000_0() {
; CHECK-LABEL: @trig_preop_constfold_0x0020000000000000_0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x10000000000000, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x0010000000000000, i32 0)
ret double %val
}
define double @trig_preop_constfold_0x001fffffffffffff_0() {
; CHECK-LABEL: @trig_preop_constfold_0x001fffffffffffff_0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0xFFFFFFFFFFFFF, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x000fffffffffffff, i32 0)
ret double %val
}
define double @trig_preop_constfold_0x8020000000000000_0() {
; CHECK-LABEL: @trig_preop_constfold_0x8020000000000000_0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x8020000000000000, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x8020000000000000, i32 0)
ret double %val
}
define double @trig_preop_constfold_0x801fffffffffffff_0() {
; CHECK-LABEL: @trig_preop_constfold_0x801fffffffffffff_0(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x801FFFFFFFFFFFFF, i32 0)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x801fffffffffffff, i32 0)
ret double %val
}