[AArch64][Windows] Add llvm-readobj support for save_any_reg unwind opcode.

[efriedma]

Summary

This is primarily used for Arm64EC, but it could be used for other non-standard calling conventions. The testcase is based on an Arm64EC thunk generated by MSVC.

The name save_any_reg comes from Microsoft documentation, but the full encoding isn't specified there; this is reverse-engineered from the behavior of the unwinder. (Thanks to Martin Storsjö for his example of how to write simple unwinder testcases by directly calling RtlVirtualUnwind.)

[mstorsjo]

LGTM, great work on reverse engineering this instruction!

I guess it would be useful to send a PR to the unwind info docs, to document your findings here too (even if the llvm-readobj code here is good enough documentation for our purposes here).

llvm/test/tools/llvm-readobj/COFF/arm64-unwind-save_any_reg.s

25

Would it be good to include cases with d registers and non-paired opcodes too?

[efriedma]

re: documentation, let's see what Microsoft says about your current patch. I mean, I'm willing to help writing up, but only if they're actually interested in taking changes.

llvm/test/tools/llvm-readobj/COFF/arm64-unwind-save_any_reg.s

25

I'm very confident the current testcase is correct because the decoded opcodes match what MSVC actually generates. I'd be less confident about other testcases... but I can add some extra tests to ensure the decoding doesn't blow up, at least.

[mstorsjo]

In D135196#3835407, @efriedma wrote:

re: documentation, let's see what Microsoft says about your current patch. I mean, I'm willing to help writing up, but only if they're actually interested in taking changes.

Ok, let's see how that one fares. OTOH, this one actually seems at least acknowledged in their other documentation, but who knows what their status/intent is wrt PAC.

Earlier I've had success with getting fixes merged in their docs, for inconsistencies/inaccuracies in the stuff that they do have documented though, but the review was fairly slow.

llvm/test/tools/llvm-readobj/COFF/arm64-unwind-save_any_reg.s

+// REQUIRES: aarch64-registered-target
+// RUN: llvm-mc -filetype=obj -triple aarch64-windows %s -o %t.o
+// RUN: llvm-readobj --unwind %t.o | FileCheck --strict-whitespace %s
+
+//CHECK:           Prologue [
+//CHECK-NEXT:        0xe1                ; mov fp, sp
+//CHECK-NEXT:        0x83                ; stp x29, x30, [sp, #-32]!
+//CHECK-NEXT:        0xe6                ; save next
+//CHECK-NEXT:        0xe6                ; save next
+//CHECK-NEXT:        0xe6                ; save next
+//CHECK-NEXT:        0xe6                ; save next
+//CHECK-NEXT:        0xe76689            ; stp q6, q7, [sp, #-160]!
+//CHECK-NEXT:        0xe4                ; end
+//CHECK-NEXT:      ]
+//CHECK-NEXT:      EpilogueScopes [
+//CHECK-NEXT:        EpilogueScope {
+//CHECK-NEXT:          StartOffset: 12
+//CHECK-NEXT:          EpilogueStartIndex: 10
+//CHECK-NEXT:          Opcodes [
+//CHECK-NEXT:            0x83                ; ldp x29, x30, [sp], #32
+//CHECK-NEXT:            0xe74e88            ; ldp q14, q15, [sp, #128]
+//CHECK-NEXT:            0xe74c86            ; ldp q12, q13, [sp, #96]
+//CHECK-NEXT:            0xe74a84            ; ldp q10, q11, [sp, #64]
+//CHECK-NEXT:            0xe74882            ; ldp q8, q9, [sp, #32]
+//CHECK-NEXT:            0xe76689            ; ldp q6, q7, [sp], #160
+//CHECK-NEXT:            0xe3                ; nop
+//CHECK-NEXT:            0xe3                ; nop
+//CHECK-NEXT:            0xe4                ; end
+//CHECK-NEXT:          ]
+//CHECK-NEXT:        }
+//CHECK-NEXT:      ]
+
+.section .pdata,"dr"
+        .long func@IMGREL
+        .long "$unwind$func"@IMGREL
+
+        .text
+        .globl  func
+func:
+        stp q6, q7, [sp, #-160]!
+        stp q8, q9, [sp, #32]
+        stp q10, q11, [sp, #64]
+        stp q12, q13, [sp, #96]
+        stp q14, q15, [sp, #128]
+        stp x29, x30, [sp, #-32]!
+        mov x29, sp
+        str x0, [sp, #16]
+        str x9, [sp, #24]
+        ldr x0, [sp, #16]
+        ldr x8, [sp, #24]
+        blr x8
+        ldp x29, x30, [sp], #32
+        ldp q14, q15, [sp, #128]
+        ldp q12, q13, [sp, #96]
+        ldp q10, q11, [sp, #64]
+        ldp q8, q9, [sp, #32]
+        ldp q6, q7, [sp], #160
+        nop
+        ldr x16, [x16]
+        br  x16
+
+.section .xdata,"dr"
+"$unwind$func":
+.byte 0x15, 0x00, 0x40, 0x40
+.byte 0x0c, 0x00, 0x80, 0x02
+.byte 0xe1, 0x83, 0xe6, 0xe6
+.byte 0xe6, 0xe6, 0xe7, 0x66
+.byte 0x89, 0xe4, 0x83, 0xe7
+.byte 0x4e, 0x88, 0xe7, 0x4c
+.byte 0x86, 0xe7, 0x4a, 0x84
+.byte 0xe7, 0x48, 0x82, 0xe7
+.byte 0x66, 0x89, 0xe3, 0xe3
+.byte 0xe4, 0xe3, 0xe3, 0xe3

llvm/tools/llvm-readobj/ARMWinEHPrinter.h

class Decoder {
   bool opcode_nop(const uint8_t *Opcodes, unsigned &Offset, unsigned Length,
                   bool Prologue);
   bool opcode_end(const uint8_t *Opcodes, unsigned &Offset, unsigned Length,
                   bool Prologue);
   bool opcode_end_c(const uint8_t *Opcodes, unsigned &Offset, unsigned Length,
                     bool Prologue);
   bool opcode_save_next(const uint8_t *Opcodes, unsigned &Offset,
                         unsigned Length, bool Prologue);
+  bool opcode_save_any_reg(const uint8_t *Opcodes, unsigned &Offset,
+                           unsigned Length, bool Prologue);
   bool opcode_trap_frame(const uint8_t *Opcodes, unsigned &Offset,
                          unsigned Length, bool Prologue);
   bool opcode_machine_frame(const uint8_t *Opcodes, unsigned &Offset,
                             unsigned Length, bool Prologue);
   bool opcode_context(const uint8_t *Opcodes, unsigned &Offset, unsigned Length,
                       bool Prologue);
   bool opcode_clear_unwound_to_call(const uint8_t *Opcodes, unsigned &Offset,
                                     unsigned Length, bool Prologue);

llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp

const Decoder::RingEntry Decoder::Ring[] = {
   { 0xff, 0xfa, 4, &Decoder::opcode_11111010 },  // UOP_STACK_RESTORE (32-bit)
   { 0xff, 0xfb, 1, &Decoder::opcode_11111011 },  // UOP_NOP (16-bit)
   { 0xff, 0xfc, 1, &Decoder::opcode_11111100 },  // UOP_NOP (32-bit)
   { 0xff, 0xfd, 1, &Decoder::opcode_11111101 },  // UOP_NOP (16-bit) / END
   { 0xff, 0xfe, 1, &Decoder::opcode_11111110 },  // UOP_NOP (32-bit) / END
   { 0xff, 0xff, 1, &Decoder::opcode_11111111 },  // UOP_END
 };
 
-
 // Unwind opcodes for ARM64.
 // https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
 const Decoder::RingEntry Decoder::Ring64[] = {
-  { 0xe0, 0x00, 1, &Decoder::opcode_alloc_s },
-  { 0xe0, 0x20, 1, &Decoder::opcode_save_r19r20_x },
-  { 0xc0, 0x40, 1, &Decoder::opcode_save_fplr },
-  { 0xc0, 0x80, 1, &Decoder::opcode_save_fplr_x },
-  { 0xf8, 0xc0, 2, &Decoder::opcode_alloc_m },
-  { 0xfc, 0xc8, 2, &Decoder::opcode_save_regp },
-  { 0xfc, 0xcc, 2, &Decoder::opcode_save_regp_x },
-  { 0xfc, 0xd0, 2, &Decoder::opcode_save_reg },
-  { 0xfe, 0xd4, 2, &Decoder::opcode_save_reg_x },
-  { 0xfe, 0xd6, 2, &Decoder::opcode_save_lrpair },
-  { 0xfe, 0xd8, 2, &Decoder::opcode_save_fregp },
-  { 0xfe, 0xda, 2, &Decoder::opcode_save_fregp_x },
-  { 0xfe, 0xdc, 2, &Decoder::opcode_save_freg },
-  { 0xff, 0xde, 2, &Decoder::opcode_save_freg_x },
-  { 0xff, 0xe0, 4, &Decoder::opcode_alloc_l },
-  { 0xff, 0xe1, 1, &Decoder::opcode_setfp },
-  { 0xff, 0xe2, 2, &Decoder::opcode_addfp },
-  { 0xff, 0xe3, 1, &Decoder::opcode_nop },
-  { 0xff, 0xe4, 1, &Decoder::opcode_end },
-  { 0xff, 0xe5, 1, &Decoder::opcode_end_c },
-  { 0xff, 0xe6, 1, &Decoder::opcode_save_next },
-  { 0xff, 0xe8, 1, &Decoder::opcode_trap_frame },
-  { 0xff, 0xe9, 1, &Decoder::opcode_machine_frame },
-  { 0xff, 0xea, 1, &Decoder::opcode_context },
-  { 0xff, 0xec, 1, &Decoder::opcode_clear_unwound_to_call },
+    {0xe0, 0x00, 1, &Decoder::opcode_alloc_s},
+    {0xe0, 0x20, 1, &Decoder::opcode_save_r19r20_x},
+    {0xc0, 0x40, 1, &Decoder::opcode_save_fplr},
+    {0xc0, 0x80, 1, &Decoder::opcode_save_fplr_x},
+    {0xf8, 0xc0, 2, &Decoder::opcode_alloc_m},
+    {0xfc, 0xc8, 2, &Decoder::opcode_save_regp},
+    {0xfc, 0xcc, 2, &Decoder::opcode_save_regp_x},
+    {0xfc, 0xd0, 2, &Decoder::opcode_save_reg},
+    {0xfe, 0xd4, 2, &Decoder::opcode_save_reg_x},
+    {0xfe, 0xd6, 2, &Decoder::opcode_save_lrpair},
+    {0xfe, 0xd8, 2, &Decoder::opcode_save_fregp},
+    {0xfe, 0xda, 2, &Decoder::opcode_save_fregp_x},
+    {0xfe, 0xdc, 2, &Decoder::opcode_save_freg},
+    {0xff, 0xde, 2, &Decoder::opcode_save_freg_x},
+    {0xff, 0xe0, 4, &Decoder::opcode_alloc_l},
+    {0xff, 0xe1, 1, &Decoder::opcode_setfp},
+    {0xff, 0xe2, 2, &Decoder::opcode_addfp},
+    {0xff, 0xe3, 1, &Decoder::opcode_nop},
+    {0xff, 0xe4, 1, &Decoder::opcode_end},
+    {0xff, 0xe5, 1, &Decoder::opcode_end_c},
+    {0xff, 0xe6, 1, &Decoder::opcode_save_next},
+    {0xff, 0xe7, 3, &Decoder::opcode_save_any_reg},
+    {0xff, 0xe8, 1, &Decoder::opcode_trap_frame},
+    {0xff, 0xe9, 1, &Decoder::opcode_machine_frame},
+    {0xff, 0xea, 1, &Decoder::opcode_context},
+    {0xff, 0xec, 1, &Decoder::opcode_clear_unwound_to_call},
 };
 
 static void printRange(raw_ostream &OS, ListSeparator &LS, unsigned First,
                        unsigned Last, char Letter) {
   if (First == Last)
     OS << LS << Letter << First;
   else
     OS << LS << Letter << First << "-" << Letter << Last;
if (Prologue)
     SW.startLine() << format("0x%02x                ; save next\n", OC[Offset]);
   else
     SW.startLine() << format("0x%02x                ; restore next\n",
                              OC[Offset]);
   ++Offset;
   return false;
 }
 
+bool Decoder::opcode_save_any_reg(const uint8_t *OC, unsigned &Offset,
+                                  unsigned Length, bool Prologue) {
+  // Whether the instruction has writeback
+  bool Writeback = (OC[Offset + 1] & 0x20) == 0x20;
+  // Whether the instruction is paired.  (Paired instructions are required
+  // to save/restore adjacent registers.)
+  bool Paired = (OC[Offset + 1] & 0x40) == 0x40;
+  // The kind of register saved:
+  // - 0 is an x register
+  // - 1 is the low half of a q register
+  // - 2 is a whole q register
+  int RegKind = (OC[Offset + 2] & 0xC0) >> 6;
+  // Encoded register name (0 -> x0/q0, 1 -> x1/q1, etc.)
+  int Reg = OC[Offset + 1] & 0x1F;
+  // Encoded stack offset of load/store instruction; decoding varies by mode.
+  int StackOffset = OC[Offset + 2] & 0x3F;
+  if (Writeback)
+    StackOffset++;
+  if (!Writeback && !Paired && RegKind != 2)
+    StackOffset *= 8;
+  else
+    StackOffset *= 16;
+
+  SW.startLine() << format("0x%02x%02x%02x            ; ", OC[Offset],
+                           OC[Offset + 1], OC[Offset + 2]);
+
+  // Verify the encoding is in a form we understand.  The high bit of the first
+  // byte, and mode 3 for the register kind are apparently reserved.  The
+  // encoded register must refer to a valid register.
+  int MaxReg = 0x1F;
+  if (Paired)
+    --MaxReg;
+  if (RegKind == 0)
+    --MaxReg;
+  if ((OC[Offset + 1] & 0x80) == 0x80 || RegKind == 3 || Reg > MaxReg) {
+    SW.getOStream() << "invalid save_any_reg encoding\n";
+    Offset += 3;
+    return false;
+  }
+
+  if (Paired) {
+    if (Prologue)
+      SW.getOStream() << "stp ";
+    else
+      SW.getOStream() << "ldp ";
+  } else {
+    if (Prologue)
+      SW.getOStream() << "str ";
+    else
+      SW.getOStream() << "ldr ";
+  }
+
+  char RegChar = 'x';
+  if (RegKind == 1) {
+    RegChar = 'd';
+  } else if (RegKind == 2) {
+    RegChar = 'q';
+  }
+
+  if (Paired)
+    SW.getOStream() << format("%c%d, %c%d, ", RegChar, Reg, RegChar, Reg + 1);
+  else
+    SW.getOStream() << format("%c%d, ", RegChar, Reg);
+
+  if (Writeback) {
+    if (Prologue)
+      SW.getOStream() << format("[sp, #-%d]!\n", StackOffset);
+    else
+      SW.getOStream() << format("[sp], #%d\n", StackOffset);
+  } else {
+    SW.getOStream() << format("[sp, #%d]\n", StackOffset);
+  }
+
+  Offset += 3;
+  return false;
+}
+
 bool Decoder::opcode_trap_frame(const uint8_t *OC, unsigned &Offset,
                                 unsigned Length, bool Prologue) {
   SW.startLine() << format("0x%02x                ; trap frame\n", OC[Offset]);
   ++Offset;
   return false;
 }
 
 bool Decoder::opcode_machine_frame(const uint8_t *OC, unsigned &Offset,