[GlobalISel] Add computeNumSignBits() support for compares.

[aemerson]

Summary

Doing so allows G_SEXT_INREG to be combined away for many vector cases.

[arsenm]

LGTM

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

case TargetOpcode::G_UMULO: {
     if (MI.getOperand(1).getReg() == R) {
       if (TL.getBooleanContents(DstTy.isVector(), false) ==
           TargetLowering::ZeroOrNegativeOneBooleanContent)
         return TyBits;
     }
 
     break;
   }
+  case TargetOpcode::G_FCMP:
+  case TargetOpcode::G_ICMP: {
+    bool IsFP = Opcode == TargetOpcode::G_FCMP;
+    if (TyBits == 1)
+      break;
+    auto BC = TL.getBooleanContents(DstTy.isVector(), IsFP);
+    if (BC == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
+      return TyBits; // All bits are sign bits.
+    if (BC == TargetLowering::ZeroOrOneBooleanContent)
+      return TyBits - 1; // Every always-zero bit is a sign bit.
+    break;
+  }
   case TargetOpcode::G_INTRINSIC:
   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
   default: {
     unsigned NumBits =
       TL.computeNumSignBitsForTargetInstr(*this, R, DemandedElts, MRI, Depth);
     if (NumBits > 1)
       FirstAnswer = std::max(FirstAnswer, NumBits);
     break;

llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll

 ; SDAG-NEXT:    uzp2 v0.8h, v0.8h, v3.8h
 ; SDAG-NEXT:    add v0.8h, v0.8h, v1.8h
 ; SDAG-NEXT:    ushl v0.8h, v0.8h, v2.8h
 ; SDAG-NEXT:    ret
 ;
 ; GISEL-LABEL: combine_vec_udiv_nonuniform:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI1_4
-; GISEL-NEXT:    adrp x9, .LCPI1_0
+; GISEL-NEXT:    adrp x9, .LCPI1_5
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI1_4]
 ; GISEL-NEXT:    adrp x8, .LCPI1_3
-; GISEL-NEXT:    ldr q5, [x9, :lo12:.LCPI1_0]
 ; GISEL-NEXT:    neg v1.8h, v1.8h
 ; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI1_3]
 ; GISEL-NEXT:    adrp x8, .LCPI1_2
 ; GISEL-NEXT:    ushl v1.8h, v0.8h, v1.8h
 ; GISEL-NEXT:    umull2 v3.4s, v1.8h, v2.8h
 ; GISEL-NEXT:    umull v1.4s, v1.4h, v2.4h
 ; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI1_2]
-; GISEL-NEXT:    adrp x8, .LCPI1_5
+; GISEL-NEXT:    adrp x8, .LCPI1_1
 ; GISEL-NEXT:    uzp2 v1.8h, v1.8h, v3.8h
 ; GISEL-NEXT:    sub v3.8h, v0.8h, v1.8h
 ; GISEL-NEXT:    umull2 v4.4s, v3.8h, v2.8h
 ; GISEL-NEXT:    umull v2.4s, v3.4h, v2.4h
-; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI1_5]
-; GISEL-NEXT:    adrp x8, .LCPI1_1
-; GISEL-NEXT:    cmeq v3.8h, v3.8h, v5.8h
+; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI1_1]
+; GISEL-NEXT:    adrp x8, .LCPI1_0
+; GISEL-NEXT:    neg v3.8h, v3.8h
 ; GISEL-NEXT:    uzp2 v2.8h, v2.8h, v4.8h
-; GISEL-NEXT:    ldr q4, [x8, :lo12:.LCPI1_1]
-; GISEL-NEXT:    shl v3.8h, v3.8h, #15
+; GISEL-NEXT:    ldr q4, [x9, :lo12:.LCPI1_5]
+; GISEL-NEXT:    ldr q5, [x8, :lo12:.LCPI1_0]
 ; GISEL-NEXT:    add v1.8h, v2.8h, v1.8h
-; GISEL-NEXT:    neg v2.8h, v4.8h
-; GISEL-NEXT:    ushl v1.8h, v1.8h, v2.8h
-; GISEL-NEXT:    sshr v2.8h, v3.8h, #15
+; GISEL-NEXT:    cmeq v2.8h, v4.8h, v5.8h
+; GISEL-NEXT:    ushl v1.8h, v1.8h, v3.8h
 ; GISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; GISEL-NEXT:    ret
   %1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768>
   ret <8 x i16> %1
 }
 
 define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
 ; SDAG-LABEL: combine_vec_udiv_nonuniform2:

 ; SDAG-NEXT:    uzp2 v0.8h, v0.8h, v1.8h
 ; SDAG-NEXT:    ldr q1, [x8, :lo12:.LCPI2_2]
 ; SDAG-NEXT:    ushl v0.8h, v0.8h, v1.8h
 ; SDAG-NEXT:    ret
 ;
 ; GISEL-LABEL: combine_vec_udiv_nonuniform2:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI2_3
-; GISEL-NEXT:    adrp x9, .LCPI2_4
-; GISEL-NEXT:    adrp x10, .LCPI2_0
+; GISEL-NEXT:    adrp x9, .LCPI2_1
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI2_3]
 ; GISEL-NEXT:    adrp x8, .LCPI2_2
-; GISEL-NEXT:    ldr q4, [x10, :lo12:.LCPI2_0]
+; GISEL-NEXT:    ldr q4, [x9, :lo12:.LCPI2_1]
 ; GISEL-NEXT:    neg v1.8h, v1.8h
 ; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI2_2]
-; GISEL-NEXT:    adrp x8, .LCPI2_1
+; GISEL-NEXT:    adrp x8, .LCPI2_4
 ; GISEL-NEXT:    ushl v1.8h, v0.8h, v1.8h
+; GISEL-NEXT:    neg v4.8h, v4.8h
 ; GISEL-NEXT:    umull2 v3.4s, v1.8h, v2.8h
-; GISEL-NEXT:    ldr q5, [x8, :lo12:.LCPI2_1]
 ; GISEL-NEXT:    umull v1.4s, v1.4h, v2.4h
-; GISEL-NEXT:    ldr q2, [x9, :lo12:.LCPI2_4]
-; GISEL-NEXT:    cmeq v2.8h, v2.8h, v4.8h
+; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI2_4]
+; GISEL-NEXT:    adrp x8, .LCPI2_0
 ; GISEL-NEXT:    uzp2 v1.8h, v1.8h, v3.8h
-; GISEL-NEXT:    neg v3.8h, v5.8h
-; GISEL-NEXT:    shl v2.8h, v2.8h, #15
-; GISEL-NEXT:    ushl v1.8h, v1.8h, v3.8h
-; GISEL-NEXT:    sshr v2.8h, v2.8h, #15
+; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI2_0]
+; GISEL-NEXT:    cmeq v2.8h, v2.8h, v3.8h
+; GISEL-NEXT:    ushl v1.8h, v1.8h, v4.8h
 ; GISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; GISEL-NEXT:    ret
   %1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>
   ret <8 x i16> %1
 }
 
 define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {
 ; SDAG-LABEL: combine_vec_udiv_nonuniform3:
 ; SDAG:       // %bb.0:
 ; SDAG-NEXT:    adrp x8, .LCPI3_0
 ; SDAG-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
 ; SDAG-NEXT:    adrp x8, .LCPI3_1
 ; SDAG-NEXT:    umull2 v2.4s, v0.8h, v1.8h
 ; SDAG-NEXT:    umull v1.4s, v0.4h, v1.4h
 ; SDAG-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
 ; SDAG-NEXT:    sub v0.8h, v0.8h, v1.8h
 ; SDAG-NEXT:    usra v1.8h, v0.8h, #1
 ; SDAG-NEXT:    ldr q0, [x8, :lo12:.LCPI3_1]
 ; SDAG-NEXT:    ushl v0.8h, v1.8h, v0.8h
 ; SDAG-NEXT:    ret
 ;
 ; GISEL-LABEL: combine_vec_udiv_nonuniform3:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI3_2
-; GISEL-NEXT:    adrp x9, .LCPI3_0
+; GISEL-NEXT:    adrp x9, .LCPI3_3
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI3_2]
-; GISEL-NEXT:    adrp x8, .LCPI3_3
-; GISEL-NEXT:    ldr q3, [x9, :lo12:.LCPI3_0]
+; GISEL-NEXT:    adrp x8, .LCPI3_1
+; GISEL-NEXT:    ldr q4, [x9, :lo12:.LCPI3_3]
 ; GISEL-NEXT:    umull2 v2.4s, v0.8h, v1.8h
 ; GISEL-NEXT:    umull v1.4s, v0.4h, v1.4h
 ; GISEL-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
-; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI3_3]
-; GISEL-NEXT:    adrp x8, .LCPI3_1
-; GISEL-NEXT:    cmeq v2.8h, v2.8h, v3.8h
-; GISEL-NEXT:    sub v4.8h, v0.8h, v1.8h
-; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI3_1]
-; GISEL-NEXT:    shl v2.8h, v2.8h, #15
-; GISEL-NEXT:    usra v1.8h, v4.8h, #1
-; GISEL-NEXT:    neg v3.8h, v3.8h
-; GISEL-NEXT:    sshr v2.8h, v2.8h, #15
-; GISEL-NEXT:    ushl v1.8h, v1.8h, v3.8h
+; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI3_1]
+; GISEL-NEXT:    adrp x8, .LCPI3_0
+; GISEL-NEXT:    neg v2.8h, v2.8h
+; GISEL-NEXT:    sub v3.8h, v0.8h, v1.8h
+; GISEL-NEXT:    usra v1.8h, v3.8h, #1
+; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI3_0]
+; GISEL-NEXT:    ushl v1.8h, v1.8h, v2.8h
+; GISEL-NEXT:    cmeq v2.8h, v4.8h, v3.8h
 ; GISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; GISEL-NEXT:    ret
   %1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127>
   ret <8 x i16> %1
 }
 
 define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
 ; SDAG-LABEL: combine_vec_udiv_nonuniform4:

 ; SDAG-NEXT:    and v1.16b, v1.16b, v3.16b
 ; SDAG-NEXT:    and v0.16b, v0.16b, v2.16b
 ; SDAG-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; SDAG-NEXT:    ret
 ;
 ; GISEL-LABEL: combine_vec_udiv_nonuniform4:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI4_2
-; GISEL-NEXT:    adrp x9, .LCPI4_0
+; GISEL-NEXT:    adrp x9, .LCPI4_1
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI4_2]
 ; GISEL-NEXT:    adrp x8, .LCPI4_3
-; GISEL-NEXT:    ldr q4, [x9, :lo12:.LCPI4_0]
+; GISEL-NEXT:    ldr q4, [x9, :lo12:.LCPI4_1]
 ; GISEL-NEXT:    umull2 v2.8h, v0.16b, v1.16b
 ; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI4_3]
 ; GISEL-NEXT:    umull v1.8h, v0.8b, v1.8b
-; GISEL-NEXT:    adrp x8, .LCPI4_1
-; GISEL-NEXT:    cmeq v3.16b, v3.16b, v4.16b
+; GISEL-NEXT:    adrp x8, .LCPI4_0
+; GISEL-NEXT:    neg v4.16b, v4.16b
 ; GISEL-NEXT:    uzp2 v1.16b, v1.16b, v2.16b
-; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI4_1]
-; GISEL-NEXT:    shl v3.16b, v3.16b, #7
-; GISEL-NEXT:    neg v2.16b, v2.16b
-; GISEL-NEXT:    ushl v1.16b, v1.16b, v2.16b
-; GISEL-NEXT:    sshr v2.16b, v3.16b, #7
+; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI4_0]
+; GISEL-NEXT:    cmeq v2.16b, v3.16b, v2.16b
+; GISEL-NEXT:    ushl v1.16b, v1.16b, v4.16b
 ; GISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; GISEL-NEXT:    ret
   %div = udiv <16 x i8> %x, <i8 -64, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %div
 }
 
 define <8 x i16> @pr38477(<8 x i16> %a0) {
 ; SDAG-LABEL: pr38477:

 ; SDAG-NEXT:    and v0.16b, v0.16b, v2.16b
 ; SDAG-NEXT:    and v1.16b, v1.16b, v4.16b
 ; SDAG-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; SDAG-NEXT:    ret
 ;
 ; GISEL-LABEL: pr38477:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI5_3
-; GISEL-NEXT:    adrp x9, .LCPI5_0
+; GISEL-NEXT:    adrp x9, .LCPI5_4
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI5_3]
 ; GISEL-NEXT:    adrp x8, .LCPI5_2
-; GISEL-NEXT:    ldr q5, [x9, :lo12:.LCPI5_0]
 ; GISEL-NEXT:    umull2 v2.4s, v0.8h, v1.8h
 ; GISEL-NEXT:    umull v1.4s, v0.4h, v1.4h
 ; GISEL-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
 ; GISEL-NEXT:    ldr q2, [x8, :lo12:.LCPI5_2]
-; GISEL-NEXT:    adrp x8, .LCPI5_4
+; GISEL-NEXT:    adrp x8, .LCPI5_1
 ; GISEL-NEXT:    sub v3.8h, v0.8h, v1.8h
 ; GISEL-NEXT:    umull2 v4.4s, v3.8h, v2.8h
 ; GISEL-NEXT:    umull v2.4s, v3.4h, v2.4h
-; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI5_4]
-; GISEL-NEXT:    adrp x8, .LCPI5_1
-; GISEL-NEXT:    cmeq v3.8h, v3.8h, v5.8h
+; GISEL-NEXT:    ldr q3, [x8, :lo12:.LCPI5_1]
+; GISEL-NEXT:    adrp x8, .LCPI5_0
+; GISEL-NEXT:    neg v3.8h, v3.8h
 ; GISEL-NEXT:    uzp2 v2.8h, v2.8h, v4.8h
-; GISEL-NEXT:    ldr q4, [x8, :lo12:.LCPI5_1]
-; GISEL-NEXT:    shl v3.8h, v3.8h, #15
+; GISEL-NEXT:    ldr q4, [x9, :lo12:.LCPI5_4]
+; GISEL-NEXT:    ldr q5, [x8, :lo12:.LCPI5_0]
 ; GISEL-NEXT:    add v1.8h, v2.8h, v1.8h
-; GISEL-NEXT:    neg v2.8h, v4.8h
-; GISEL-NEXT:    ushl v1.8h, v1.8h, v2.8h
-; GISEL-NEXT:    sshr v2.8h, v3.8h, #15
+; GISEL-NEXT:    cmeq v2.8h, v4.8h, v5.8h
+; GISEL-NEXT:    ushl v1.8h, v1.8h, v3.8h
 ; GISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; GISEL-NEXT:    ret
   %1 = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31>
   ret <8 x i16> %1
 }

llvm/test/CodeGen/AArch64/arm64-vabs.ll

 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: uabdl4s_rdx_i32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v2, #0000000000000000
 ; GISEL-NEXT:    usubl.4s v0, v0, v1
 ; GISEL-NEXT:    cmgt.4s v1, v2, v0
 ; GISEL-NEXT:    neg.4s v2, v0
-; GISEL-NEXT:    shl.4s v1, v1, #31
-; GISEL-NEXT:    sshr.4s v1, v1, #31
 ; GISEL-NEXT:    bit.16b v0, v2, v1
 ; GISEL-NEXT:    addv.4s s0, v0
 ; GISEL-NEXT:    fmov w0, s0
 ; GISEL-NEXT:    ret
 
 ; GISel doesn't match this pattern yet.
   %aext = zext <4 x i16> %a to <4 x i32>
   %bext = zext <4 x i16> %b to <4 x i32>

 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: uabdl2d_rdx_i64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v2, #0000000000000000
 ; GISEL-NEXT:    usubl.2d v0, v0, v1
 ; GISEL-NEXT:    cmgt.2d v1, v2, v0
 ; GISEL-NEXT:    neg.2d v2, v0
-; GISEL-NEXT:    shl.2d v1, v1, #63
-; GISEL-NEXT:    sshr.2d v1, v1, #63
 ; GISEL-NEXT:    bit.16b v0, v2, v1
 ; GISEL-NEXT:    addp.2d d0, v0
 ; GISEL-NEXT:    fmov x0, d0
 ; GISEL-NEXT:    ret
 
 ; GISel doesn't match this pattern yet
   %aext = zext <2 x i32> %a to <2 x i64>
   %bext = zext <2 x i32> %b to <2 x i64>

 ; DAG-NEXT:    abs.2s v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern1:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.2s v2, v0
 ; GISEL-NEXT:    cmge.2s v1, v0, v1
-; GISEL-NEXT:    shl.2s v1, v1, #31
-; GISEL-NEXT:    sshr.2s v1, v1, #31
 ; GISEL-NEXT:    bif.8b v0, v2, v1
 ; GISEL-NEXT:    ret
 
   %tmp1neg = sub <2 x i32> zeroinitializer, %a
   %b = icmp sge <2 x i32> %a, zeroinitializer
   %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
   ret <2 x i32> %abs
 }
 
 define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
 ; DAG-LABEL: abspattern2:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    abs.4h v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern2:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.4h v2, v0
 ; GISEL-NEXT:    cmgt.4h v1, v0, v1
-; GISEL-NEXT:    shl.4h v1, v1, #15
-; GISEL-NEXT:    sshr.4h v1, v1, #15
 ; GISEL-NEXT:    bif.8b v0, v2, v1
 ; GISEL-NEXT:    ret
 ; For GlobalISel, this generates terrible code until we can pattern match this to abs.
 
   %tmp1neg = sub <4 x i16> zeroinitializer, %a
   %b = icmp sgt <4 x i16> %a, zeroinitializer
   %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
   ret <4 x i16> %abs
 }
 
 define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
 ; DAG-LABEL: abspattern3:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    abs.8b v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern3:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.8b v2, v0
 ; GISEL-NEXT:    cmgt.8b v1, v1, v0
-; GISEL-NEXT:    shl.8b v1, v1, #7
-; GISEL-NEXT:    sshr.8b v1, v1, #7
 ; GISEL-NEXT:    bit.8b v0, v2, v1
 ; GISEL-NEXT:    ret
 
   %tmp1neg = sub <8 x i8> zeroinitializer, %a
   %b = icmp slt <8 x i8> %a, zeroinitializer
   %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
   ret <8 x i8> %abs
 }
 
 define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
 ; DAG-LABEL: abspattern4:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    abs.4s v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern4:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.4s v2, v0
 ; GISEL-NEXT:    cmge.4s v1, v0, v1
-; GISEL-NEXT:    shl.4s v1, v1, #31
-; GISEL-NEXT:    sshr.4s v1, v1, #31
 ; GISEL-NEXT:    bif.16b v0, v2, v1
 ; GISEL-NEXT:    ret
 
   %tmp1neg = sub <4 x i32> zeroinitializer, %a
   %b = icmp sge <4 x i32> %a, zeroinitializer
   %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
   ret <4 x i32> %abs
 }
 
 define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
 ; DAG-LABEL: abspattern5:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    abs.8h v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern5:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.8h v2, v0
 ; GISEL-NEXT:    cmgt.8h v1, v0, v1
-; GISEL-NEXT:    shl.8h v1, v1, #15
-; GISEL-NEXT:    sshr.8h v1, v1, #15
 ; GISEL-NEXT:    bif.16b v0, v2, v1
 ; GISEL-NEXT:    ret
 
   %tmp1neg = sub <8 x i16> zeroinitializer, %a
   %b = icmp sgt <8 x i16> %a, zeroinitializer
   %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
   ret <8 x i16> %abs
 }
 
 define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
 ; DAG-LABEL: abspattern6:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    abs.16b v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern6:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.16b v2, v0
 ; GISEL-NEXT:    cmgt.16b v1, v1, v0
-; GISEL-NEXT:    shl.16b v1, v1, #7
-; GISEL-NEXT:    sshr.16b v1, v1, #7
 ; GISEL-NEXT:    bit.16b v0, v2, v1
 ; GISEL-NEXT:    ret
 
   %tmp1neg = sub <16 x i8> zeroinitializer, %a
   %b = icmp slt <16 x i8> %a, zeroinitializer
   %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
   ret <16 x i8> %abs
 }
 
 define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
 ; DAG-LABEL: abspattern7:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    abs.2d v0, v0
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: abspattern7:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v1, #0000000000000000
 ; GISEL-NEXT:    neg.2d v2, v0
 ; GISEL-NEXT:    cmge.2d v1, v1, v0
-; GISEL-NEXT:    shl.2d v1, v1, #63
-; GISEL-NEXT:    sshr.2d v1, v1, #63
 ; GISEL-NEXT:    bit.16b v0, v2, v1
 ; GISEL-NEXT:    ret
 
   %tmp1neg = sub <2 x i64> zeroinitializer, %a
   %b = icmp sle <2 x i64> %a, zeroinitializer
   %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
   ret <2 x i64> %abs
 }
 
 define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
 ; DAG-LABEL: uabd_i32:
 ; DAG:       // %bb.0:
 ; DAG-NEXT:    sabdl.2d v0, v0, v1
 ; DAG-NEXT:    ret
 ;
 ; GISEL-LABEL: uabd_i32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi.2d v2, #0000000000000000
 ; GISEL-NEXT:    ssubl.2d v0, v0, v1
 ; GISEL-NEXT:    cmgt.2d v1, v2, v0
 ; GISEL-NEXT:    neg.2d v2, v0
-; GISEL-NEXT:    shl.2d v1, v1, #63
-; GISEL-NEXT:    sshr.2d v1, v1, #63
 ; GISEL-NEXT:    bit.16b v0, v2, v1
 ; GISEL-NEXT:    ret
   %aext = sext <2 x i32> %a to <2 x i64>
   %bext = sext <2 x i32> %b to <2 x i64>
   %abdiff = sub nsw <2 x i64> %aext, %bext
   %abcmp = icmp slt <2 x i64> %abdiff, zeroinitializer
   %ababs = sub nsw <2 x i64> zeroinitializer, %abdiff
   %absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %abdiff
; CHECK-NEXT:    ret
   %aext = sext <2 x i64> %a to <2 x i128>
   %bext = sext <2 x i64> %b to <2 x i128>
   %abdiff = sub nsw <2 x i128> %aext, %bext
   %abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer
   %ababs = sub nsw <2 x i128> zeroinitializer, %abdiff
   %absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff
   ret <2 x i128> %absel
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; FALLBACK: {{.*}}

llvm/test/CodeGen/AArch64/min-max.ll

 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %a, <1 x i64> %b)
   ret <1 x i64> %c
 }
 
 declare <2 x i64> @llvm.smax.v2i64(<2 x i64> %a, <2 x i64> %b) readnone
 
 define <2 x i64> @smax2i64(<2 x i64> %a, <2 x i64> %b) {
-; CHECK-ISEL-LABEL: smax2i64:
-; CHECK-ISEL:       // %bb.0:
-; CHECK-ISEL-NEXT:    cmgt v2.2d, v0.2d, v1.2d
-; CHECK-ISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-ISEL-NEXT:    ret
-;
-; CHECK-GLOBAL-LABEL: smax2i64:
-; CHECK-GLOBAL:       // %bb.0:
-; CHECK-GLOBAL-NEXT:    cmgt v2.2d, v0.2d, v1.2d
-; CHECK-GLOBAL-NEXT:    shl v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-GLOBAL-NEXT:    ret
+; CHECK-LABEL: smax2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmgt v2.2d, v0.2d, v1.2d
+; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %c = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i64> %c
 }
 
 declare <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b) readnone
 
 define void @smax4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
 ; CHECK-ISEL-LABEL: smax4i64:
 ; CHECK-ISEL:       // %bb.0:
 ; CHECK-ISEL-NEXT:    cmgt v4.2d, v1.2d, v3.2d
 ; CHECK-ISEL-NEXT:    cmgt v5.2d, v0.2d, v2.2d
 ; CHECK-ISEL-NEXT:    bif v1.16b, v3.16b, v4.16b
 ; CHECK-ISEL-NEXT:    bif v0.16b, v2.16b, v5.16b
 ; CHECK-ISEL-NEXT:    stp q0, q1, [x0]
 ; CHECK-ISEL-NEXT:    ret
 ;
 ; CHECK-GLOBAL-LABEL: smax4i64:
 ; CHECK-GLOBAL:       // %bb.0:
 ; CHECK-GLOBAL-NEXT:    cmgt v4.2d, v0.2d, v2.2d
 ; CHECK-GLOBAL-NEXT:    cmgt v5.2d, v1.2d, v3.2d
-; CHECK-GLOBAL-NEXT:    shl v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    shl v5.2d, v5.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v5.2d, v5.2d, #63
 ; CHECK-GLOBAL-NEXT:    bif v0.16b, v2.16b, v4.16b
 ; CHECK-GLOBAL-NEXT:    bif v1.16b, v3.16b, v5.16b
 ; CHECK-GLOBAL-NEXT:    stp q0, q1, [x0]
 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b)
   store <4 x i64> %c, <4 x i64>* %p
   ret void
 }

 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %a, <1 x i64> %b)
   ret <1 x i64> %c
 }
 
 declare <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b) readnone
 
 define <2 x i64> @umax2i64(<2 x i64> %a, <2 x i64> %b) {
-; CHECK-ISEL-LABEL: umax2i64:
-; CHECK-ISEL:       // %bb.0:
-; CHECK-ISEL-NEXT:    cmhi v2.2d, v0.2d, v1.2d
-; CHECK-ISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-ISEL-NEXT:    ret
-;
-; CHECK-GLOBAL-LABEL: umax2i64:
-; CHECK-GLOBAL:       // %bb.0:
-; CHECK-GLOBAL-NEXT:    cmhi v2.2d, v0.2d, v1.2d
-; CHECK-GLOBAL-NEXT:    shl v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-GLOBAL-NEXT:    ret
+; CHECK-LABEL: umax2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmhi v2.2d, v0.2d, v1.2d
+; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %c = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i64> %c
 }
 
 declare <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b) readnone
 
 define void @umax4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
 ; CHECK-ISEL-LABEL: umax4i64:
 ; CHECK-ISEL:       // %bb.0:
 ; CHECK-ISEL-NEXT:    cmhi v4.2d, v1.2d, v3.2d
 ; CHECK-ISEL-NEXT:    cmhi v5.2d, v0.2d, v2.2d
 ; CHECK-ISEL-NEXT:    bif v1.16b, v3.16b, v4.16b
 ; CHECK-ISEL-NEXT:    bif v0.16b, v2.16b, v5.16b
 ; CHECK-ISEL-NEXT:    stp q0, q1, [x0]
 ; CHECK-ISEL-NEXT:    ret
 ;
 ; CHECK-GLOBAL-LABEL: umax4i64:
 ; CHECK-GLOBAL:       // %bb.0:
 ; CHECK-GLOBAL-NEXT:    cmhi v4.2d, v0.2d, v2.2d
 ; CHECK-GLOBAL-NEXT:    cmhi v5.2d, v1.2d, v3.2d
-; CHECK-GLOBAL-NEXT:    shl v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    shl v5.2d, v5.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v5.2d, v5.2d, #63
 ; CHECK-GLOBAL-NEXT:    bif v0.16b, v2.16b, v4.16b
 ; CHECK-GLOBAL-NEXT:    bif v1.16b, v3.16b, v5.16b
 ; CHECK-GLOBAL-NEXT:    stp q0, q1, [x0]
 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b)
   store <4 x i64> %c, <4 x i64>* %p
   ret void
 }

 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %a, <1 x i64> %b)
   ret <1 x i64> %c
 }
 
 declare <2 x i64> @llvm.smin.v2i64(<2 x i64> %a, <2 x i64> %b) readnone
 
 define <2 x i64> @smin2i64(<2 x i64> %a, <2 x i64> %b) {
-; CHECK-ISEL-LABEL: smin2i64:
-; CHECK-ISEL:       // %bb.0:
-; CHECK-ISEL-NEXT:    cmgt v2.2d, v1.2d, v0.2d
-; CHECK-ISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-ISEL-NEXT:    ret
-;
-; CHECK-GLOBAL-LABEL: smin2i64:
-; CHECK-GLOBAL:       // %bb.0:
-; CHECK-GLOBAL-NEXT:    cmgt v2.2d, v1.2d, v0.2d
-; CHECK-GLOBAL-NEXT:    shl v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-GLOBAL-NEXT:    ret
+; CHECK-LABEL: smin2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmgt v2.2d, v1.2d, v0.2d
+; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %c = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i64> %c
 }
 
 declare <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b) readnone
 
 define void @smin4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
 ; CHECK-ISEL-LABEL: smin4i64:
 ; CHECK-ISEL:       // %bb.0:
 ; CHECK-ISEL-NEXT:    cmgt v4.2d, v3.2d, v1.2d
 ; CHECK-ISEL-NEXT:    cmgt v5.2d, v2.2d, v0.2d
 ; CHECK-ISEL-NEXT:    bif v1.16b, v3.16b, v4.16b
 ; CHECK-ISEL-NEXT:    bif v0.16b, v2.16b, v5.16b
 ; CHECK-ISEL-NEXT:    stp q0, q1, [x0]
 ; CHECK-ISEL-NEXT:    ret
 ;
 ; CHECK-GLOBAL-LABEL: smin4i64:
 ; CHECK-GLOBAL:       // %bb.0:
 ; CHECK-GLOBAL-NEXT:    cmgt v4.2d, v2.2d, v0.2d
 ; CHECK-GLOBAL-NEXT:    cmgt v5.2d, v3.2d, v1.2d
-; CHECK-GLOBAL-NEXT:    shl v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    shl v5.2d, v5.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v5.2d, v5.2d, #63
 ; CHECK-GLOBAL-NEXT:    bif v0.16b, v2.16b, v4.16b
 ; CHECK-GLOBAL-NEXT:    bif v1.16b, v3.16b, v5.16b
 ; CHECK-GLOBAL-NEXT:    stp q0, q1, [x0]
 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b)
   store <4 x i64> %c, <4 x i64>* %p
   ret void
 }

 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %a, <1 x i64> %b)
   ret <1 x i64> %c
 }
 
 declare <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b) readnone
 
 define <2 x i64> @umin2i64(<2 x i64> %a, <2 x i64> %b) {
-; CHECK-ISEL-LABEL: umin2i64:
-; CHECK-ISEL:       // %bb.0:
-; CHECK-ISEL-NEXT:    cmhi v2.2d, v1.2d, v0.2d
-; CHECK-ISEL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-ISEL-NEXT:    ret
-;
-; CHECK-GLOBAL-LABEL: umin2i64:
-; CHECK-GLOBAL:       // %bb.0:
-; CHECK-GLOBAL-NEXT:    cmhi v2.2d, v1.2d, v0.2d
-; CHECK-GLOBAL-NEXT:    shl v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v2.2d, v2.2d, #63
-; CHECK-GLOBAL-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-GLOBAL-NEXT:    ret
+; CHECK-LABEL: umin2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmhi v2.2d, v1.2d, v0.2d
+; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %c = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i64> %c
 }
 
 declare <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b) readnone
 
 define void @umin4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
 ; CHECK-ISEL-LABEL: umin4i64:
 ; CHECK-ISEL:       // %bb.0:
 ; CHECK-ISEL-NEXT:    cmhi v4.2d, v3.2d, v1.2d
 ; CHECK-ISEL-NEXT:    cmhi v5.2d, v2.2d, v0.2d
 ; CHECK-ISEL-NEXT:    bif v1.16b, v3.16b, v4.16b
 ; CHECK-ISEL-NEXT:    bif v0.16b, v2.16b, v5.16b
 ; CHECK-ISEL-NEXT:    stp q0, q1, [x0]
 ; CHECK-ISEL-NEXT:    ret
 ;
 ; CHECK-GLOBAL-LABEL: umin4i64:
 ; CHECK-GLOBAL:       // %bb.0:
 ; CHECK-GLOBAL-NEXT:    cmhi v4.2d, v2.2d, v0.2d
 ; CHECK-GLOBAL-NEXT:    cmhi v5.2d, v3.2d, v1.2d
-; CHECK-GLOBAL-NEXT:    shl v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    shl v5.2d, v5.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v4.2d, v4.2d, #63
-; CHECK-GLOBAL-NEXT:    sshr v5.2d, v5.2d, #63
 ; CHECK-GLOBAL-NEXT:    bif v0.16b, v2.16b, v4.16b
 ; CHECK-GLOBAL-NEXT:    bif v1.16b, v3.16b, v5.16b
 ; CHECK-GLOBAL-NEXT:    stp q0, q1, [x0]
 ; CHECK-GLOBAL-NEXT:    ret
   %c = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b)
   store <4 x i64> %c, <4 x i64>* %p
   ret void
 }

llvm/test/CodeGen/AArch64/neon-compare-instructions.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon %s -o - | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 %s -o - | FileCheck %s --check-prefix=GISEL
 
 define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmeq8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmeq16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmeq4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmeq8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmeq2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmeq4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmeq2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeq2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmne8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmne16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmne4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.4h, v0.4h, v1.4h
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmne8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.8h, v0.8h, v1.8h
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmne2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmne4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmne2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmne2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmeq v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmgt8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmgt16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmgt4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmgt8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmgt2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmgt4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmgt2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgt2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmlt8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmlt16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmlt4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.4h, v1.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmlt8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmlt2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmlt4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; LT implemented as GT, so check reversed operands.
 define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmlt2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlt2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmgt v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmge8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmge16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmge4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmge8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmge2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmge4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmge2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmge2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmle8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmle16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmle4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.4h, v1.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmle8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmle2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmle4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; LE implemented as GE, so check reversed operands.
 define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmle2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmle2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmge v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmhi8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmhi16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmhi4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmhi8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmhi2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmhi4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmhi2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhi2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmlo8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmlo16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmlo4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.4h, v1.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmlo8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmlo2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmlo4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmlo2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlo2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhi v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmhs8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmhs16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmhs4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmhs8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmhs2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmhs4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmhs2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhs2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmls8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <8 x i8> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmls16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <16 x i8> %A, %B;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmls4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.4h, v1.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <4 x i16> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmls8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <8 x i16> %A, %B;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmls2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <2 x i32> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmls4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <4 x i32> %A, %B;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmls2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhs v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmls2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmhs v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <2 x i64> %A, %B;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: cmtst8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    cmeq v0.8b, v0.8b, v2.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = and <8 x i8> %A, %B
   %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
   %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
   ret <8 x i8> %tmp5
 }
 
 define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
 ; CHECK-LABEL: cmtst16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    cmeq v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = and <16 x i8> %A, %B
   %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
   %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
   ret <16 x i8> %tmp5
 }
 
 define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: cmtst4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    cmeq v0.4h, v0.4h, v2.4h
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = and <4 x i16> %A, %B
   %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
   %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
   ret <4 x i16> %tmp5
 }
 
 define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: cmtst8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    cmeq v0.8h, v0.8h, v2.8h
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = and <8 x i16> %A, %B
   %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
   %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
   ret <8 x i16> %tmp5
 }
 
 define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: cmtst2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    cmeq v0.2s, v0.2s, v2.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = and <2 x i32> %A, %B
   %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
   %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
   ret <2 x i32> %tmp5
 }
 
 define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: cmtst4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    cmeq v0.4s, v0.4s, v2.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = and <4 x i32> %A, %B
   %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
   %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
   ret <4 x i32> %tmp5
 }
 
 define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: cmtst2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmtst2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v2.2d, #0000000000000000
 ; GISEL-NEXT:    and v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    cmeq v0.2d, v0.2d, v2.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = and <2 x i64> %A, %B
   %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
   %tmp5 = sext <2 x i1> %tmp4 to <2 x i64>
   ret <2 x i64> %tmp5
 }
 
 
 
 define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmeqz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.8b, v0.8b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmeqz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmeqz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4h, v0.4h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmeqz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.8h, v0.8h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmeqz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.2s, v0.2s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmeqz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmeqz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.2d, v0.2d, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmeqz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmgez8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.8b, v0.8b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmgez16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.16b, v0.16b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmgez4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.4h, v0.4h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmgez8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.8h, v0.8h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmgez2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.2s, v0.2s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmgez4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.4s, v0.4s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmgez2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmge v0.2d, v0.2d, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgez2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) {

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.8b, v0.8b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmgtz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmgtz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.4h, v0.4h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmgtz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.8h, v0.8h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmgtz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.2s, v0.2s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmgtz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.4s, v0.4s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmgtz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmgt v0.2d, v0.2d, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmgtz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmlez8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.8b, v0.8b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmlez16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.16b, v0.16b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmlez4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.4h, v0.4h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmlez8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.8h, v0.8h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmlez2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.2s, v0.2s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmlez4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.4s, v0.4s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmlez2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmle v0.2d, v0.2d, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlez2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmge v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmltz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.8b, v0.8b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmltz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmltz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.4h, v0.4h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmltz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.8h, v0.8h, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmltz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmltz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.4s, v0.4s, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmltz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmlt v0.2d, v0.2d, #0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmltz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmgt v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmneqz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.8b, v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmneqz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.16b, v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmneqz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.4h, v0.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.4h, v0.4h, v1.4h
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmneqz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.8h, v0.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.8h, v0.8h, v1.8h
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmneqz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.2s, v0.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmneqz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.4s, v0.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmneqz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.2d, v0.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmneqz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmeq v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmhsz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8b, #2
 ; CHECK-NEXT:    cmhs v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI126_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI126_0]
 ; GISEL-NEXT:    cmhs v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmhsz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.16b, #2
 ; CHECK-NEXT:    cmhs v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI127_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI127_0]
 ; GISEL-NEXT:    cmhs v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmhsz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4h, #2
 ; CHECK-NEXT:    cmhs v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI128_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI128_0]
 ; GISEL-NEXT:    cmhs v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2>
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmhsz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8h, #2
 ; CHECK-NEXT:    cmhs v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI129_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI129_0]
 ; GISEL-NEXT:    cmhs v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmhsz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2s, #2
 ; CHECK-NEXT:    cmhs v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI130_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI130_0]
 ; GISEL-NEXT:    cmhs v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <2 x i32> %A, <i32 2, i32 2>
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmhsz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4s, #2
 ; CHECK-NEXT:    cmhs v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI131_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI131_0]
 ; GISEL-NEXT:    cmhs v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmhsz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #2
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    cmhs v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhsz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI132_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI132_0]
 ; GISEL-NEXT:    cmhs v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2>
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmhiz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8b, #1
 ; CHECK-NEXT:    cmhi v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI133_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI133_0]
 ; GISEL-NEXT:    cmhi v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <8 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmhiz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.16b, #1
 ; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI134_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI134_0]
 ; GISEL-NEXT:    cmhi v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <16 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmhiz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4h, #1
 ; CHECK-NEXT:    cmhi v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI135_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI135_0]
 ; GISEL-NEXT:    cmhi v0.4h, v0.4h, v1.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <4 x i16> %A, <i16 1, i16 1, i16 1, i16 1>
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmhiz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8h, #1
 ; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI136_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI136_0]
 ; GISEL-NEXT:    cmhi v0.8h, v0.8h, v1.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <8 x i16> %A, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmhiz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2s, #1
 ; CHECK-NEXT:    cmhi v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI137_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI137_0]
 ; GISEL-NEXT:    cmhi v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <2 x i32> %A, <i32 1, i32 1>
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmhiz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4s, #1
 ; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI138_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI138_0]
 ; GISEL-NEXT:    cmhi v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmhiz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmhiz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI139_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI139_0]
 ; GISEL-NEXT:    cmhi v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1>
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmlsz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmlsz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmlsz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.4h, v1.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmlsz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmlsz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmlsz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; LS implemented as HS, so check reversed operands.
 define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmlsz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    cmhs v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmlsz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    movi v1.2d, #0000000000000000
 ; GISEL-NEXT:    cmhs v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmloz8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8b, #2
 ; CHECK-NEXT:    cmhi v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz8xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI147_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI147_0]
 ; GISEL-NEXT:    cmhi v0.8b, v1.8b, v0.8b
-; GISEL-NEXT:    shl v0.8b, v0.8b, #7
-; GISEL-NEXT:    sshr v0.8b, v0.8b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
 ; CHECK-LABEL: cmloz16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.16b, #2
 ; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz16xi8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI148_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI148_0]
 ; GISEL-NEXT:    cmhi v0.16b, v1.16b, v0.16b
-; GISEL-NEXT:    shl v0.16b, v0.16b, #7
-; GISEL-NEXT:    sshr v0.16b, v0.16b, #7
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
   ret <16 x i8> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
 ; CHECK-LABEL: cmloz4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4h, #2
 ; CHECK-NEXT:    cmhi v0.4h, v1.4h, v0.4h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz4xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI149_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI149_0]
 ; GISEL-NEXT:    cmhi v0.4h, v1.4h, v0.4h
-; GISEL-NEXT:    shl v0.4h, v0.4h, #15
-; GISEL-NEXT:    sshr v0.4h, v0.4h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2>
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
   ret <4 x i16> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
 ; CHECK-LABEL: cmloz8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8h, #2
 ; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz8xi16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI150_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI150_0]
 ; GISEL-NEXT:    cmhi v0.8h, v1.8h, v0.8h
-; GISEL-NEXT:    shl v0.8h, v0.8h, #15
-; GISEL-NEXT:    sshr v0.8h, v0.8h, #15
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
 ; CHECK-LABEL: cmloz2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.2s, #2
 ; CHECK-NEXT:    cmhi v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz2xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI151_0
 ; GISEL-NEXT:    ldr d1, [x8, :lo12:.LCPI151_0]
 ; GISEL-NEXT:    cmhi v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <2 x i32> %A, <i32 2, i32 2>
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
 ; CHECK-LABEL: cmloz4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4s, #2
 ; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz4xi32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI152_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI152_0]
 ; GISEL-NEXT:    cmhi v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; LO implemented as HI, so check reversed operands.
 define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmloz2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #2
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: cmloz2xi64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    adrp x8, .LCPI153_0
 ; GISEL-NEXT:    ldr q1, [x8, :lo12:.LCPI153_0]
 ; GISEL-NEXT:    cmhi v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2>
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmoeq2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeq2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oeq <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmoeq4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeq4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oeq <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmoeq2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeq2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oeq <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmoge2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoge2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oge <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmoge4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoge4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oge <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmoge2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoge2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oge <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmogt2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogt2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ogt <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmogt4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogt4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ogt <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmogt2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogt2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ogt <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; OLE implemented as OGE, so check reversed operands.
 define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmole2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmole2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ole <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; OLE implemented as OGE, so check reversed operands.
 define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmole4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmole4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ole <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; OLE implemented as OGE, so check reversed operands.
 define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmole2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmole2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ole <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; OLE implemented as OGE, so check reversed operands.
 define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmolt2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolt2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp olt <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; OLE implemented as OGE, so check reversed operands.
 define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmolt4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolt4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp olt <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; OLE implemented as OGE, so check reversed operands.
 define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmolt2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolt2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp olt <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
 define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmone2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmone2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp one <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
 define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmone4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmone4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp one <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
 ; todo check reversed operands
 define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmone2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmone2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp one <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
 define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmord2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmord2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ord <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
 define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmord4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmord4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ord <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
 define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmord2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmord2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ord <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
 define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmuno2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuno2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uno <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
 define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmuno4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuno4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uno <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
 define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmuno2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuno2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uno <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
 define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmueq2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueq2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ueq <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
 define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmueq4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueq4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ueq <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
 define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmueq2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueq2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ueq <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
 define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmuge2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuge2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uge <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
 define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmuge4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuge4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uge <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
 define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmuge2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuge2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uge <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
 define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmugt2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugt2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ugt <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
 define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmugt4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugt4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ugt <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmugt2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugt2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ugt <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ULE implemented as !OGT.
 define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmule2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmule2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ule <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ULE implemented as !OGT.
 define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmule4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmule4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ule <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ULE implemented as !OGT.
 define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmule2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmule2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ule <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ULT implemented as !OGE.
 define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmult2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmult2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ult <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ULT implemented as !OGE.
 define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmult4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmult4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ult <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ULT implemented as !OGE.
 define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmult2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmult2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ult <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UNE = !OEQ.
 define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmune2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmune2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp une <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UNE = !OEQ.
 define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmune4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmune4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp une <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UNE = !OEQ.
 define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmune2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmune2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp une <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmoeqz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeqz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmoeqz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeqz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmoeqz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeqz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 define <2 x i32> @fcmogez2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmogez2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogez2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oge <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmogez4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmogez4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogez4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oge <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmogez2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmogez2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogez2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp oge <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmogtz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogtz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmogtz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogtz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmogtz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogtz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmoltz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoltz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp olt <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmoltz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoltz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp olt <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmoltz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoltz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp olt <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmolez2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmolez2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolez2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ole <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmolez4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmolez4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolez4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ole <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmolez2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmolez2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolez2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ole <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ONE with zero = OLT | OGT
 define <2 x i32> @fcmonez2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmonez2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v1.2s, v0.2s, #0.0
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmonez2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp one <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ONE with zero = OLT | OGT
 define <4 x i32> @fcmonez4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmonez4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v1.4s, v0.4s, #0.0
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmonez4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp one <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ONE with zero = OLT | OGT
 define <2 x i64> @fcmonez2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmonez2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v1.2d, v0.2d, #0.0
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmonez2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp one <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ORD with zero = OLT | OGE
 define <2 x i32> @fcmordz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmordz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmordz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ord <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ORD with zero = OLT | OGE
 define <4 x i32> @fcmordz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmordz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmordz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ord <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ORD with zero = OLT | OGE
 define <2 x i64> @fcmordz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmordz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmordz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ord <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UEQ with zero = !ONE = !(OLT |OGT)
 define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmueqz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v1.2s, v0.2s, #0.0
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueqz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UEQ with zero = !ONE = !(OLT |OGT)
 define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmueqz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v1.4s, v0.4s, #0.0
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueqz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UEQ with zero = !ONE = !(OLT |OGT)
 define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmueqz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v1.2d, v0.2d, #0.0
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueqz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UGE with zero = !OLT
 define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmugez2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugez2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uge <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UGE with zero = !OLT
 define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmugez4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugez4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uge <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UGE with zero = !OLT
 define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmugez2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugez2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uge <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UGT with zero = !OLE
 define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmugtz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugtz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UGT with zero = !OLE
 define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmugtz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugtz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UGT with zero = !OLE
 define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmugtz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugtz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ULT with zero = !OGE
 define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmultz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmultz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ult <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmultz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmultz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ult <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmultz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmultz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ult <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ULE with zero = !OGT
 define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmulez2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmulez2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ule <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; ULE with zero = !OGT
 define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmulez4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmulez4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ule <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; ULE with zero = !OGT
 define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmulez2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmulez2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp ule <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UNE with zero = !OEQ with zero
 define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmunez2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunez2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp une <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UNE with zero = !OEQ with zero
 define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmunez4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunez4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp une <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UNE with zero = !OEQ with zero
 define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmunez2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunez2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp une <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; UNO with zero = !ORD = !(OLT | OGE)
 define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
 ; CHECK-LABEL: fcmunoz2xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunoz2xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uno <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 ; UNO with zero = !ORD = !(OLT | OGE)
 define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
 ; CHECK-LABEL: fcmunoz4xfloat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunoz4xfloat:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uno <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 ; UNO with zero = !ORD = !(OLT | OGE)
 define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
 ; CHECK-LABEL: fcmunoz2xdouble:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunoz2xdouble:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp uno <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 
 }
 
 define <2 x i32> @fcmoeq2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmoeq2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeq2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oeq <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoeq4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmoeq4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeq4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oeq <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmoeq2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmoeq2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeq2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oeq <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoge2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmoge2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoge2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oge <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoge4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmoge4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoge4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oge <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmoge2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmoge2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoge2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oge <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmogt2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmogt2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogt2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ogt <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmogt4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmogt4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogt4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ogt <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmogt2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmogt2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogt2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ogt <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmole2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmole2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmole2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ole <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmole4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmole4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmole4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ole <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmole2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmole2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmole2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ole <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmolt2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmolt2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolt2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast olt <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmolt4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmolt4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolt4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast olt <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmolt2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmolt2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolt2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast olt <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmone2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmone2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmone2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast one <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmone4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmone4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmone4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast one <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmone2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmone2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmone2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast one <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmord2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmord2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmord2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ord <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmord4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmord4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmord4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ord <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmord2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmord2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmord2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ord <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 define <2 x i32> @fcmuno2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmuno2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuno2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uno <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmuno4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmuno4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuno4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uno <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmuno2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmuno2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuno2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uno <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmueq2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmueq2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueq2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v2.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ueq <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmueq4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmueq4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueq4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ueq <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmueq2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmueq2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueq2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v2.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v2.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ueq <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmuge2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmuge2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuge2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uge <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmuge4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmuge4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuge4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uge <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmuge2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmuge2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmuge2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uge <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmugt2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmugt2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugt2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v1.2s, v0.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ugt <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmugt4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmugt4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugt4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v1.4s, v0.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ugt <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmugt2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmugt2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugt2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v1.2d, v0.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ugt <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmule2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmule2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmule2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ule <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmule4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmule4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmule4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ule <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmule2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmule2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmule2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ule <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmult2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmult2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v1.2s, v0.2s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmult2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ult <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmult4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmult4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmult4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ult <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmult2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmult2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v1.2d, v0.2d
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmult2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ult <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmune2xfloat_fast(<2 x float> %A, <2 x float> %B) {
 ; CHECK-LABEL: fcmune2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmune2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, v1.2s
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast une <2 x float> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmune4xfloat_fast(<4 x float> %A, <4 x float> %B) {
 ; CHECK-LABEL: fcmune4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmune4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast une <4 x float> %A, %B
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmune2xdouble_fast(<2 x double> %A, <2 x double> %B) {
 ; CHECK-LABEL: fcmune2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmune2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, v1.2d
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast une <2 x double> %A, %B
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoeqz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmoeqz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeqz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oeq <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoeqz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmoeqz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeqz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oeq <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmoeqz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmoeqz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoeqz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oeq <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 
 define <2 x i32> @fcmogez2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmogez2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogez2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oge <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmogez4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmogez4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogez4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oge <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmogez2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmogez2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogez2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast oge <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmogtz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmogtz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogtz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ogt <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmogtz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmogtz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogtz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ogt <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 define <2 x i64> @fcmogtz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmogtz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmogtz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ogt <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmoltz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmoltz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoltz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast olt <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmoltz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmoltz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoltz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast olt <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmoltz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmoltz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmoltz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast olt <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmolez2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmolez2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolez2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2s, v0.2s, #0.0
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ole <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmolez4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmolez4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolez4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.4s, v0.4s, #0.0
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ole <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmolez2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmolez2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmolez2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2d, v0.2d, #0.0
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ole <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmonez2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmonez2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmonez2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast one <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmonez4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmonez4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmonez4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast one <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmonez2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmonez2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmonez2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast one <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmordz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmordz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmordz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ord <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmordz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmordz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmordz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ord <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmordz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmordz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmordz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ord <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmueqz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmueqz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueqz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ueq <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmueqz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmueqz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueqz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ueq <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmueqz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmueqz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmueqz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ueq <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmugez2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmugez2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugez2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uge <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmugez4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmugez4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugez4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uge <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmugez2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmugez2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugez2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uge <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmugtz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmugtz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugtz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ugt <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmugtz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmugtz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugtz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ugt <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmugtz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmugtz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmugtz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmle v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ugt <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmultz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmultz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmultz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ult <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmultz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmultz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmultz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ult <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmultz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmultz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmultz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ult <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 ; ULE with zero = !OGT
 define <2 x i32> @fcmulez2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmulez2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmulez2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ule <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmulez4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmulez4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmulez4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ule <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmulez2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmulez2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmle v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmulez2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast ule <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmunez2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmunez2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunez2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast une <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmunez4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmunez4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunez4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast une <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmunez2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmunez2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunez2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmeq v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast une <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i32> @fcmunoz2xfloat_fast(<2 x float> %A) {
 ; CHECK-LABEL: fcmunoz2xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; CHECK-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    mvn v0.8b, v0.8b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunoz2xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2s, v0.2s, #0.0
 ; GISEL-NEXT:    fcmlt v0.2s, v0.2s, #0.0
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mvn v0.8b, v0.8b
-; GISEL-NEXT:    shl v0.2s, v0.2s, #31
-; GISEL-NEXT:    sshr v0.2s, v0.2s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uno <2 x float> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
   ret <2 x i32> %tmp4
 }
 
 define <4 x i32> @fcmunoz4xfloat_fast(<4 x float> %A) {
 ; CHECK-LABEL: fcmunoz4xfloat_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; CHECK-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunoz4xfloat_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.4s, v0.4s, #0.0
 ; GISEL-NEXT:    fcmlt v0.4s, v0.4s, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.4s, v0.4s, #31
-; GISEL-NEXT:    sshr v0.4s, v0.4s, #31
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uno <4 x float> %A, zeroinitializer
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @fcmunoz2xdouble_fast(<2 x double> %A) {
 ; CHECK-LABEL: fcmunoz2xdouble_fast:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; CHECK-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: fcmunoz2xdouble_fast:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcmge v1.2d, v0.2d, #0.0
 ; GISEL-NEXT:    fcmlt v0.2d, v0.2d, #0.0
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mvn v0.16b, v0.16b
-; GISEL-NEXT:    shl v0.2d, v0.2d, #63
-; GISEL-NEXT:    sshr v0.2d, v0.2d, #63
 ; GISEL-NEXT:    ret
   %tmp3 = fcmp fast uno <2 x double> %A, zeroinitializer
   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 
 }
 
 ; Test SETCC fast-math flags are propagated when combining zext(setcc).

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) {
   Register CopyTrunc7 = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
   EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));
   EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));
 }
 
+TEST_F(AArch64GISelMITest, TestNumSignBitsCmp) {
+  StringRef MIRString =
+      "  %v1:_(<4 x s32>) = G_IMPLICIT_DEF\n"
+      "  %v2:_(<4 x s32>) = G_IMPLICIT_DEF\n"
+      "  %s1:_(s64) = G_IMPLICIT_DEF\n"
+      "  %s2:_(s64) = G_IMPLICIT_DEF\n"
+      "  %cmp:_(<4 x s32>) = G_FCMP floatpred(ogt), %v1, %v2\n"
+      "  %cpy1:_(<4 x s32>) = COPY %cmp\n"
+      "  %cmp2:_(<4 x s32>) = G_ICMP intpred(eq), %v1, %v2\n"
+      "  %cpy2:_(<4 x s32>) = COPY %cmp2\n"
+      "  %cmp3:_(s32) = G_FCMP floatpred(ogt), %s1, %s2\n"
+      "  %cpy3:_(s32) = COPY %cmp3\n"
+      "  %cmp4:_(s32) = G_ICMP intpred(eq), %s1, %s2\n"
+      "  %cpy4:_(s32) = COPY %cmp4\n";
+
+  setUp(MIRString);
+  if (!TM)
+    return;
+  Register CopyVecFCMP = Copies[Copies.size() - 4];
+  Register CopyVecICMP = Copies[Copies.size() - 3];
+  Register CopyScalarFCMP = Copies[Copies.size() - 2];
+  Register CopyScalarICMP = Copies[Copies.size() - 1];
+
+  GISelKnownBits Info(*MF);
+  EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecFCMP));
+  EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecICMP));
+  EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarFCMP));
+  EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarICMP));
+}
+
 TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {
   StringRef MIRString =
     "  %3:_(<4 x s32>) = G_IMPLICIT_DEF\n"
     "  %4:_(s32) = G_IMPLICIT_DEF\n"
     "  %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
     "  %6:_(s32) = COPY %5\n"
 
     "  %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"