[LegalizeTypes] Use structured bindings to replace std::tie in some cases.

[craig.topper]

Summary

This simplies code where we declared two variables and immediately tied them.

I've focused on the most common case of splitting into Lo and Hi
SDValues or EVTs when splitting vectors.

[RKSimon]

I've no objections although I don't know how this matches with the coding standard regarding auto (which was written prior to c++17 in the codebase)? Ideally we'd mention structured bindings in the section on use of auto.

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
case TargetLowering::TypeSplitVector: {
     EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
                                    NumElts.divideCoefficientBy(2));
     if (N->getOpcode() == ISD::TRUNCATE) {
       EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
       EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
     } else {
       assert(N->getOpcode() == ISD::VP_TRUNCATE &&
              "Expected VP_TRUNCATE opcode");
-      SDValue MaskLo, MaskHi, EVLLo, EVLHi;
-      std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
-      std::tie(EVLLo, EVLHi) =
+      auto [MaskLo, MaskHi] = SplitMask(N->getOperand(1));
+      auto [EVLLo, EVLHi] =
           DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
       EOp1 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp1, MaskLo, EVLLo);
       EOp2 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp2, MaskHi, EVLHi);
     }
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
   }
   // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
   // targets.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (N->getNumOperands() == 2) {
     Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
     Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
     return;
   }
 
   assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
   assert(N->isVPOpcode() && "Expected VP opcode");
 
-  SDValue MaskLo, MaskHi;
-  std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(2));
+  auto [MaskLo, MaskHi] = SplitMask(N->getOperand(2));
 
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) =
-      DAG.SplitEVL(N->getOperand(3), N->getValueType(0), dl);
+  auto [EVLLo, EVLHi] = DAG.SplitEVL(N->getOperand(3), N->getValueType(0), dl);
 
   Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(),
                    {LHSLo, RHSLo, MaskLo, EVLLo}, Flags);
   Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(),
                    {LHSHi, RHSHi, MaskHi, EVLHi}, Flags);
 }
 
 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
if (N->getNumOperands() == 3) {
     Lo = DAG.getNode(Opcode, dl, Op0Lo.getValueType(), Op0Lo, Op1Lo, Op2Lo, Flags);
     Hi = DAG.getNode(Opcode, dl, Op0Hi.getValueType(), Op0Hi, Op1Hi, Op2Hi, Flags);
     return;
   }
 
   assert(N->getNumOperands() == 5 && "Unexpected number of operands!");
   assert(N->isVPOpcode() && "Expected VP opcode");
 
-  SDValue MaskLo, MaskHi;
-  std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
+  auto [MaskLo, MaskHi] = SplitMask(N->getOperand(3));
 
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) =
-      DAG.SplitEVL(N->getOperand(4), N->getValueType(0), dl);
+  auto [EVLLo, EVLHi] = DAG.SplitEVL(N->getOperand(4), N->getValueType(0), dl);
 
   Lo = DAG.getNode(Opcode, dl, Op0Lo.getValueType(),
                    {Op0Lo, Op1Lo, Op2Lo, MaskLo, EVLLo}, Flags);
   Hi = DAG.getNode(Opcode, dl, Op0Hi.getValueType(),
                    {Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags);
 }
 
 void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
   Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Op2,
                    N->getFlags());
 }
 
 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
   // We know the result is a vector.  The input may be either a vector or a
   // scalar value.
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
   SDLoc dl(N);
 
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
 
   // Handle some special cases efficiently.
   switch (getTypeAction(InVT)) {
   case TargetLowering::TypeLegal:
void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
   if (DAG.getDataLayout().isBigEndian())
     std::swap(Lo, Hi);
   Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
   Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
 }
 
 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
                                                 SDValue &Hi) {
-  EVT LoVT, HiVT;
   SDLoc dl(N);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
   unsigned LoNumElts = LoVT.getVectorNumElements();
   SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
   Lo = DAG.getBuildVector(LoVT, dl, LoOps);
 
   SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
   Hi = DAG.getBuildVector(HiVT, dl, HiOps);
 }
 
 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
                                                   SDValue &Hi) {
   assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
   SDLoc dl(N);
   unsigned NumSubvectors = N->getNumOperands() / 2;
   if (NumSubvectors == 1) {
     Lo = N->getOperand(0);
     Hi = N->getOperand(1);
     return;
   }
 
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
   Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
 
   SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
   Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
 }
 
 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
                                                      SDValue &Hi) {
   SDValue Vec = N->getOperand(0);
   SDValue Idx = N->getOperand(1);
   SDLoc dl(N);
 
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
   uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
   Hi = DAG.getNode(
       ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
       DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl));
 }
 

 }
 
 void DAGTypeLegalizer::SplitVecRes_IS_FPCLASS(SDNode *N, SDValue &Lo,
                                               SDValue &Hi) {
   SDLoc DL(N);
   SDValue ArgLo, ArgHi;
   SDValue Test = N->getOperand(1);
   GetSplitVector(N->getOperand(0), ArgLo, ArgHi);
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   Lo = DAG.getNode(ISD::IS_FPCLASS, DL, LoVT, ArgLo, Test, N->getFlags());
   Hi = DAG.getNode(ISD::IS_FPCLASS, DL, HiVT, ArgHi, Test, N->getFlags());
 }
 
 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
   SDValue LHSLo, LHSHi;
   GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
   SDLoc dl(N);
 
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) =
+  auto [LoVT, HiVT] =
       DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
 
   Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
                    DAG.getValueType(LoVT));
   Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
                    DAG.getValueType(HiVT));
 }
 
 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
                                                  SDValue &Hi) {
   unsigned Opcode = N->getOpcode();
   SDValue N0 = N->getOperand(0);
 
   SDLoc dl(N);
   SDValue InLo, InHi;
 
   if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
     GetSplitVector(N0, InLo, InHi);
   else
     std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
 
   EVT InLoVT = InLo.getValueType();
   unsigned InNumElements = InLoVT.getVectorNumElements();
 
-  EVT OutLoVT, OutHiVT;
-  std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [OutLoVT, OutHiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
   unsigned OutNumElements = OutLoVT.getVectorNumElements();
   assert((2 * OutNumElements) <= InNumElements &&
          "Illegal extend vector in reg split");
 
   // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
   // input vector (i.e. we only use InLo):
   // OutLo will extend the first OutNumElements from InLo.
   // OutHi will extend the next OutNumElements from InLo.
 
   // Shuffle the elements from InLo for OutHi into the bottom elements to
   // create a 'fake' InHi.
   SmallVector<int, 8> SplitHi(InNumElements, -1);
   for (unsigned i = 0; i != OutNumElements; ++i)
     SplitHi[i] = i + OutNumElements;
   InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
 
   Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
   Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
 }
 
 void DAGTypeLegalizer::SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo,
                                               SDValue &Hi) {
   unsigned NumOps = N->getNumOperands();
   SDValue Chain = N->getOperand(0);
-  EVT LoVT, HiVT;
   SDLoc dl(N);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   SmallVector<SDValue, 4> OpsLo(NumOps);
   SmallVector<SDValue, 4> OpsHi(NumOps);
 
   // The Chain is the first operand.
   OpsLo[0] = Chain;
   OpsHi[0] = Chain;
 
SDValue DAGTypeLegalizer::UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE) {
   return DAG.getBuildVector(VecVT, dl, Scalars);
 }
 
 void DAGTypeLegalizer::SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
                                               SDValue &Lo, SDValue &Hi) {
   SDLoc dl(N);
   EVT ResVT = N->getValueType(0);
   EVT OvVT = N->getValueType(1);
-  EVT LoResVT, HiResVT, LoOvVT, HiOvVT;
-  std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT);
-  std::tie(LoOvVT, HiOvVT) = DAG.GetSplitDestVTs(OvVT);
+  auto [LoResVT, HiResVT] = DAG.GetSplitDestVTs(ResVT);
+  auto [LoOvVT, HiOvVT] = DAG.GetSplitDestVTs(OvVT);
 
   SDValue LoLHS, HiLHS, LoRHS, HiRHS;
   if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) {
     GetSplitVector(N->getOperand(0), LoLHS, HiLHS);
     GetSplitVector(N->getOperand(1), LoRHS, HiRHS);
   } else {
     std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0);
     std::tie(LoRHS, HiRHS) = DAG.SplitVectorOperand(N, 1);
void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
   // Store the new element.  This may be larger than the vector element type,
   // so use a truncating store.
   SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
   Store = DAG.getTruncStore(
       Store, dl, Elt, EltPtr, MachinePointerInfo::getUnknownStack(MF), EltVT,
       commonAlignment(SmallestAlign,
                       EltVT.getFixedSizeInBits() / 8));
 
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT);
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(VecVT);
 
   // Load the Lo part from the stack slot.
   Lo = DAG.getLoad(LoVT, dl, Store, StackPtr, PtrInfo, SmallestAlign);
 
   // Increment the pointer to the other part.
   auto Load = cast<LoadSDNode>(Lo);
   MachinePointerInfo MPI = Load->getPointerInfo();
   IncrementPointer(Load, LoVT, MPI, StackPtr);
 
   Hi = DAG.getLoad(HiVT, dl, Store, StackPtr, MPI, SmallestAlign);
 
   // If we adjusted the original type, we need to truncate the results.
   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
   if (LoVT != Lo.getValueType())
     Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo);
   if (HiVT != Hi.getValueType())
     Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
 }
 
 void DAGTypeLegalizer::SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo,
                                                SDValue &Hi) {
-  EVT LoVT, HiVT;
   SDLoc dl(N);
   assert(N->getValueType(0).isScalableVector() &&
          "Only scalable vectors are supported for STEP_VECTOR");
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
   SDValue Step = N->getOperand(0);
 
   Lo = DAG.getNode(ISD::STEP_VECTOR, dl, LoVT, Step);
 
   // Hi = Lo + (EltCnt * Step)
   EVT EltVT = Step.getValueType();
   APInt StepVal = cast<ConstantSDNode>(Step)->getAPIntValue();
   SDValue StartOfHi =
       DAG.getVScale(dl, EltVT, StepVal * LoVT.getVectorMinNumElements());
   StartOfHi = DAG.getSExtOrTrunc(StartOfHi, dl, HiVT.getVectorElementType());
   StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi);
 
   Hi = DAG.getNode(ISD::STEP_VECTOR, dl, HiVT, Step);
   Hi = DAG.getNode(ISD::ADD, dl, HiVT, Hi, StartOfHi);
 }
 
 void DAGTypeLegalizer::SplitVecRes_ScalarOp(SDNode *N, SDValue &Lo,
                                             SDValue &Hi) {
-  EVT LoVT, HiVT;
   SDLoc dl(N);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
   Lo = DAG.getNode(N->getOpcode(), dl, LoVT, N->getOperand(0));
   if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
     Hi = DAG.getUNDEF(HiVT);
   } else {
     assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode");
     Hi = Lo;
   }
 }
 
 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
                                         SDValue &Hi) {
   assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
-  EVT LoVT, HiVT;
   SDLoc dl(LD);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(LD->getValueType(0));
 
   ISD::LoadExtType ExtType = LD->getExtensionType();
   SDValue Ch = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
   EVT MemoryVT = LD->getMemoryVT();
   MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
   AAMDNodes AAInfo = LD->getAAInfo();
 
-  EVT LoMemVT, HiMemVT;
-  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
+  auto [LoMemVT, HiMemVT] = DAG.GetSplitDestVTs(MemoryVT);
 
   if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized()) {
     SDValue Value, NewChain;
     std::tie(Value, NewChain) = TLI.scalarizeVectorLoad(LD, DAG);
     std::tie(Lo, Hi) = DAG.SplitVector(Value, dl);
     ReplaceValueWith(SDValue(LD, 1), NewChain);
     return;
   }
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.
   ReplaceValueWith(SDValue(LD, 1), Ch);
 }
 
 void DAGTypeLegalizer::SplitVecRes_VP_LOAD(VPLoadSDNode *LD, SDValue &Lo,
                                            SDValue &Hi) {
   assert(LD->isUnindexed() && "Indexed VP load during type legalization!");
-  EVT LoVT, HiVT;
   SDLoc dl(LD);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(LD->getValueType(0));
 
   ISD::LoadExtType ExtType = LD->getExtensionType();
   SDValue Ch = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   SDValue Offset = LD->getOffset();
   assert(Offset.isUndef() && "Unexpected indexed variable-length load offset");
   Align Alignment = LD->getOriginalAlign();
   SDValue Mask = LD->getMask();
   SDValue EVL = LD->getVectorLength();
   EVT MemoryVT = LD->getMemoryVT();
 
-  EVT LoMemVT, HiMemVT;
   bool HiIsEmpty = false;
-  std::tie(LoMemVT, HiMemVT) =
+  auto [LoMemVT, HiMemVT] =
       DAG.GetDependentSplitDestVTs(MemoryVT, LoVT, &HiIsEmpty);
 
   // Split Mask operand
   SDValue MaskLo, MaskHi;
   if (Mask.getOpcode() == ISD::SETCC) {
     SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
   } else {
     if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
       GetSplitVector(Mask, MaskLo, MaskHi);
     else
       std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
   }
 
   // Split EVL operand
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) = DAG.SplitEVL(EVL, LD->getValueType(0), dl);
+  auto [EVLLo, EVLHi] = DAG.SplitEVL(EVL, LD->getValueType(0), dl);
 
   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
       LD->getPointerInfo(), MachineMemOperand::MOLoad,
       MemoryLocation::UnknownSize, Alignment, LD->getAAInfo(), LD->getRanges());
 
   Lo =
       DAG.getLoadVP(LD->getAddressingMode(), ExtType, LoVT, dl, Ch, Ptr, Offset,
                     MaskLo, EVLLo, LoMemVT, MMO, LD->isExpandingLoad());
void DAGTypeLegalizer::SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD,
                                                    SDValue &Lo, SDValue &Hi) {
   assert(SLD->isUnindexed() &&
          "Indexed VP strided load during type legalization!");
   assert(SLD->getOffset().isUndef() &&
          "Unexpected indexed variable-length load offset");
 
   SDLoc DL(SLD);
 
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(SLD->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(SLD->getValueType(0));
 
-  EVT LoMemVT, HiMemVT;
   bool HiIsEmpty = false;
-  std::tie(LoMemVT, HiMemVT) =
+  auto [LoMemVT, HiMemVT] =
       DAG.GetDependentSplitDestVTs(SLD->getMemoryVT(), LoVT, &HiIsEmpty);
 
   SDValue Mask = SLD->getMask();
   SDValue LoMask, HiMask;
   if (Mask.getOpcode() == ISD::SETCC) {
     SplitVecRes_SETCC(Mask.getNode(), LoMask, HiMask);
   } else {
     if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
       GetSplitVector(Mask, LoMask, HiMask);
     else
       std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
   }
 
-  SDValue LoEVL, HiEVL;
-  std::tie(LoEVL, HiEVL) =
+  auto [LoEVL, HiEVL] =
       DAG.SplitEVL(SLD->getVectorLength(), SLD->getValueType(0), DL);
 
   // Generate the low vp_strided_load
   Lo = DAG.getStridedLoadVP(
       SLD->getAddressingMode(), SLD->getExtensionType(), LoVT, DL,
       SLD->getChain(), SLD->getBasePtr(), SLD->getOffset(), SLD->getStride(),
       LoMask, LoEVL, LoMemVT, SLD->getMemOperand(), SLD->isExpandingLoad());
 
void DAGTypeLegalizer::SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD,
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.
   ReplaceValueWith(SDValue(SLD, 1), Ch);
 }
 
 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
                                          SDValue &Lo, SDValue &Hi) {
   assert(MLD->isUnindexed() && "Indexed masked load during type legalization!");
-  EVT LoVT, HiVT;
   SDLoc dl(MLD);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(MLD->getValueType(0));
 
   SDValue Ch = MLD->getChain();
   SDValue Ptr = MLD->getBasePtr();
   SDValue Offset = MLD->getOffset();
   assert(Offset.isUndef() && "Unexpected indexed masked load offset");
   SDValue Mask = MLD->getMask();
   SDValue PassThru = MLD->getPassThru();
   Align Alignment = MLD->getOriginalAlign();
   ISD::LoadExtType ExtType = MLD->getExtensionType();
 
   // Split Mask operand
   SDValue MaskLo, MaskHi;
   if (Mask.getOpcode() == ISD::SETCC) {
     SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
   } else {
     if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
       GetSplitVector(Mask, MaskLo, MaskHi);
     else
       std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
   }
 
   EVT MemoryVT = MLD->getMemoryVT();
-  EVT LoMemVT, HiMemVT;
   bool HiIsEmpty = false;
-  std::tie(LoMemVT, HiMemVT) =
+  auto [LoMemVT, HiMemVT] =
       DAG.GetDependentSplitDestVTs(MemoryVT, LoVT, &HiIsEmpty);
 
   SDValue PassThruLo, PassThruHi;
   if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
     GetSplitVector(PassThru, PassThruLo, PassThruHi);
   else
     std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
 
void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.
   ReplaceValueWith(SDValue(MLD, 1), Ch);
 
 }
 
 void DAGTypeLegalizer::SplitVecRes_Gather(MemSDNode *N, SDValue &Lo,
                                           SDValue &Hi, bool SplitSETCC) {
-  EVT LoVT, HiVT;
   SDLoc dl(N);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   SDValue Ch = N->getChain();
   SDValue Ptr = N->getBasePtr();
   struct Operands {
     SDValue Mask;
     SDValue Index;
     SDValue Scale;
   } Ops = [&]() -> Operands {
void DAGTypeLegalizer::SplitVecRes_Gather(MemSDNode *N, SDValue &Lo,
   // Split Mask operand
   SDValue MaskLo, MaskHi;
   if (SplitSETCC && Ops.Mask.getOpcode() == ISD::SETCC) {
     SplitVecRes_SETCC(Ops.Mask.getNode(), MaskLo, MaskHi);
   } else {
     std::tie(MaskLo, MaskHi) = SplitMask(Ops.Mask, dl);
   }
 
-  EVT LoMemVT, HiMemVT;
   // Split MemoryVT
-  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
+  auto [LoMemVT, HiMemVT] = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue IndexHi, IndexLo;
   if (getTypeAction(Ops.Index.getValueType()) ==
       TargetLowering::TypeSplitVector)
     GetSplitVector(Ops.Index, IndexLo, IndexHi);
   else
     std::tie(IndexLo, IndexHi) = DAG.SplitVector(Ops.Index, dl);
 
if (auto *MGT = dyn_cast<MaskedGatherSDNode>(N)) {
     Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoMemVT, dl,
                              OpsLo, MMO, IndexTy, ExtType);
 
     SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Ops.Scale};
     Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiMemVT, dl,
                              OpsHi, MMO, IndexTy, ExtType);
   } else {
     auto *VPGT = cast<VPGatherSDNode>(N);
-    SDValue EVLLo, EVLHi;
-    std::tie(EVLLo, EVLHi) =
-        DAG.SplitEVL(VPGT->getVectorLength(), MemoryVT, dl);
+    auto [EVLLo, EVLHi] = DAG.SplitEVL(VPGT->getVectorLength(), MemoryVT, dl);
 
     SDValue OpsLo[] = {Ch, Ptr, IndexLo, Ops.Scale, MaskLo, EVLLo};
     Lo = DAG.getGatherVP(DAG.getVTList(LoVT, MVT::Other), LoMemVT, dl, OpsLo,
                          MMO, VPGT->getIndexType());
 
     SDValue OpsHi[] = {Ch, Ptr, IndexHi, Ops.Scale, MaskHi, EVLHi};
     Hi = DAG.getGatherVP(DAG.getVTList(HiVT, MVT::Other), HiMemVT, dl, OpsHi,
                          MMO, VPGT->getIndexType());
void DAGTypeLegalizer::SplitVecRes_Gather(MemSDNode *N, SDValue &Lo,
   ReplaceValueWith(SDValue(N, 1), Ch);
 }
 
 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
   assert(N->getValueType(0).isVector() &&
          N->getOperand(0).getValueType().isVector() &&
          "Operand types must be vectors");
 
-  EVT LoVT, HiVT;
   SDLoc DL(N);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   // If the input also splits, handle it directly. Otherwise split it by hand.
   SDValue LL, LH, RL, RH;
   if (getTypeAction(N->getOperand(0).getValueType()) ==
       TargetLowering::TypeSplitVector)
     GetSplitVector(N->getOperand(0), LL, LH);
   else
     std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
 
   if (getTypeAction(N->getOperand(1).getValueType()) ==
       TargetLowering::TypeSplitVector)
     GetSplitVector(N->getOperand(1), RL, RH);
   else
     std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
 
   if (N->getOpcode() == ISD::SETCC) {
     Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
     Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
   } else {
     assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
-    SDValue MaskLo, MaskHi, EVLLo, EVLHi;
-    std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
-    std::tie(EVLLo, EVLHi) =
+    auto [MaskLo, MaskHi] = SplitMask(N->getOperand(3));
+    auto [EVLLo, EVLHi] =
         DAG.SplitEVL(N->getOperand(4), N->getValueType(0), DL);
     Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2), MaskLo,
                      EVLLo);
     Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2), MaskHi,
                      EVLHi);
   }
 }
 
 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
   // Get the dest types - they may not match the input types, e.g. int_to_fp.
-  EVT LoVT, HiVT;
   SDLoc dl(N);
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   // If the input also splits, handle it directly for a compile time speedup.
   // Otherwise split it by hand.
   EVT InVT = N->getOperand(0).getValueType();
   if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
     GetSplitVector(N->getOperand(0), Lo, Hi);
   else
     std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
if (Opcode == ISD::FP_ROUND) {
       Hi = DAG.getNode(Opcode, dl, HiVT, Hi, Flags);
     }
     return;
   }
 
   assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
   assert(N->isVPOpcode() && "Expected VP opcode");
 
-  SDValue MaskLo, MaskHi;
-  std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
+  auto [MaskLo, MaskHi] = SplitMask(N->getOperand(1));
 
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) =
-      DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
+  auto [EVLLo, EVLHi] = DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
 
   Lo = DAG.getNode(Opcode, dl, LoVT, {Lo, MaskLo, EVLLo}, Flags);
   Hi = DAG.getNode(Opcode, dl, HiVT, {Hi, MaskHi, EVLHi}, Flags);
 }
 
 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
                                             SDValue &Hi) {
   SDLoc dl(N);
   EVT SrcVT = N->getOperand(0).getValueType();
   EVT DestVT = N->getValueType(0);
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(DestVT);
 
   // We can do better than a generic split operation if the extend is doing
   // more than just doubling the width of the elements and the following are
   // true:
   //   - The number of vector elements is even,
   //   - the source type is legal,
   //   - the type of a split source is illegal,
   //   - the type of an extended (by doubling element size) source is legal, and
   //   - the type of that extended source when split is legal.
   //
   // This won't necessarily completely legalize the operation, but it will
   // more effectively move in the right direction and prevent falling down
   // to scalarization in many cases due to the input vector being split too
   // far.
   if (SrcVT.getVectorElementCount().isKnownEven() &&
       SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) {
     LLVMContext &Ctx = *DAG.getContext();
     EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
     EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
 
-    EVT SplitLoVT, SplitHiVT;
-    std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
+    auto [SplitLoVT, SplitHiVT] = DAG.GetSplitDestVTs(NewSrcVT);
     if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
         TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
       LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:";
                  N->dump(&DAG); dbgs() << "\n");
       if (!N->isVPOpcode()) {
         // Extend the source vector by one step.
         SDValue NewSrc =
             DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
         // Get the low and high halves of the new, extended one step, vector.
         std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
         // Extend those vector halves the rest of the way.
         Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
         Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
         return;
       }
 
       // Extend the source vector by one step.
       SDValue NewSrc =
           DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0),
                       N->getOperand(1), N->getOperand(2));
       // Get the low and high halves of the new, extended one step, vector.
       std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
 
-      SDValue MaskLo, MaskHi;
-      std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
+      auto [MaskLo, MaskHi] = SplitMask(N->getOperand(1));
 
-      SDValue EVLLo, EVLHi;
-      std::tie(EVLLo, EVLHi) =
+      auto [EVLLo, EVLHi] =
           DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
       // Extend those vector halves the rest of the way.
       Lo = DAG.getNode(N->getOpcode(), dl, LoVT, {Lo, MaskLo, EVLLo});
       Hi = DAG.getNode(N->getOpcode(), dl, HiVT, {Hi, MaskHi, EVLHi});
       return;
     }
   }
   // Fall back to the generic unary operator splitting otherwise.
void DAGTypeLegalizer::SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
 
   // Modified the chain - switch anything that used the old chain to use
   // the new one.
   ReplaceValueWith(SDValue(N, 1), Chain);
 }
 
 void DAGTypeLegalizer::SplitVecRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
                                                   SDValue &Hi) {
-  EVT DstVTLo, DstVTHi;
-  std::tie(DstVTLo, DstVTHi) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [DstVTLo, DstVTHi] = DAG.GetSplitDestVTs(N->getValueType(0));
   SDLoc dl(N);
 
   SDValue SrcLo, SrcHi;
   EVT SrcVT = N->getOperand(0).getValueType();
   if (getTypeAction(SrcVT) == TargetLowering::TypeSplitVector)
     GetSplitVector(N->getOperand(0), SrcLo, SrcHi);
   else
     std::tie(SrcLo, SrcHi) = DAG.SplitVectorOperand(N, 0);
void DAGTypeLegalizer::SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo,
   Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, InLo.getValueType(), InLo);
 }
 
 void DAGTypeLegalizer::SplitVecRes_VECTOR_SPLICE(SDNode *N, SDValue &Lo,
                                                  SDValue &Hi) {
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
-  EVT LoVT, HiVT;
-  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
+  auto [LoVT, HiVT] = DAG.GetSplitDestVTs(VT);
 
   SDValue Expanded = TLI.expandVectorSplice(N, DAG);
   Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, Expanded,
                    DAG.getVectorIdxConstant(0, DL));
   Hi =
       DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, Expanded,
                   DAG.getVectorIdxConstant(LoVT.getVectorMinNumElements(), DL));
 }
SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
   SDLoc DL(N);
   assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
 
   SDValue Lo, Hi;
   GetSplitVector(N->getOperand(0), Lo, Hi);
   assert(Lo.getValueType() == Hi.getValueType() &&
          "Lo and Hi have differing types");
 
-  EVT LoOpVT, HiOpVT;
-  std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
+  auto [LoOpVT, HiOpVT] = DAG.GetSplitDestVTs(Src0VT);
   assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
 
-  SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
-  std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
-  std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
-  std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
+  auto [LoOp0, HiOp0] = DAG.SplitVector(Src0, DL);
+  auto [LoOp1, HiOp1] = DAG.SplitVector(Src1, DL);
+  auto [LoMask, HiMask] = DAG.SplitVector(Mask, DL);
 
   SDValue LoSelect =
     DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
   SDValue HiSelect =
     DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
 
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
   EVT ResVT = N->getValueType(0);
   SDValue Lo, Hi;
   SDLoc dl(N);
 
   SDValue VecOp = N->getOperand(OpNo);
   EVT VecVT = VecOp.getValueType();
   assert(VecVT.isVector() && "Can only split reduce vector operand");
   GetSplitVector(VecOp, Lo, Hi);
-  EVT LoOpVT, HiOpVT;
-  std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
+  auto [LoOpVT, HiOpVT] = DAG.GetSplitDestVTs(VecVT);
 
   // Use the appropriate scalar instruction on the split subvectors before
   // reducing the now partially reduced smaller vector.
   unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode());
   SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
   return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE_SEQ(SDNode *N) {
   EVT ResVT = N->getValueType(0);
   SDValue Lo, Hi;
   SDLoc dl(N);
 
   SDValue AccOp = N->getOperand(0);
   SDValue VecOp = N->getOperand(1);
   SDNodeFlags Flags = N->getFlags();
 
   EVT VecVT = VecOp.getValueType();
   assert(VecVT.isVector() && "Can only split reduce vector operand");
   GetSplitVector(VecOp, Lo, Hi);
-  EVT LoOpVT, HiOpVT;
-  std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
 
   // Reduce low half.
   SDValue Partial = DAG.getNode(N->getOpcode(), dl, ResVT, AccOp, Lo, Flags);
 
   // Reduce high half, using low half result as initial value.
   return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, Hi, Flags);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
   assert(N->isVPOpcode() && "Expected VP opcode");
   assert(OpNo == 1 && "Can only split reduce vector operand");
 
   unsigned Opc = N->getOpcode();
   EVT ResVT = N->getValueType(0);
   SDValue Lo, Hi;
   SDLoc dl(N);
 
   SDValue VecOp = N->getOperand(OpNo);
   EVT VecVT = VecOp.getValueType();
   assert(VecVT.isVector() && "Can only split reduce vector operand");
   GetSplitVector(VecOp, Lo, Hi);
 
-  SDValue MaskLo, MaskHi;
-  std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(2));
+  auto [MaskLo, MaskHi] = SplitMask(N->getOperand(2));
 
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) = DAG.SplitEVL(N->getOperand(3), VecVT, dl);
+  auto [EVLLo, EVLHi] = DAG.SplitEVL(N->getOperand(3), VecVT, dl);
 
   const SDNodeFlags Flags = N->getFlags();
 
   SDValue ResLo =
       DAG.getNode(Opc, dl, ResVT, {N->getOperand(0), Lo, MaskLo, EVLLo}, Flags);
   return DAG.getNode(Opc, dl, ResVT, {ResLo, Hi, MaskHi, EVLHi}, Flags);
 }
 
if (N->isStrictFPOpcode()) {
     SDValue Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                              Hi.getValue(1));
   
     // Legalize the chain result - switch anything that used the old chain to
     // use the new one.
     ReplaceValueWith(SDValue(N, 1), Ch);
   } else if (N->getNumOperands() == 3) {
     assert(N->isVPOpcode() && "Expected VP opcode");
-    SDValue MaskLo, MaskHi, EVLLo, EVLHi;
-    std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
-    std::tie(EVLLo, EVLHi) =
+    auto [MaskLo, MaskHi] = SplitMask(N->getOperand(1));
+    auto [EVLLo, EVLHi] =
         DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
     Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo, MaskLo, EVLLo);
     Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi, MaskHi, EVLHi);
   } else {
     Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
     Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
   }
 
SDValue DAGTypeLegalizer::SplitVecOp_VP_STORE(VPStoreSDNode *N, unsigned OpNo) {
   } else {
     if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
       GetSplitVector(Mask, MaskLo, MaskHi);
     else
       std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
   }
 
   EVT MemoryVT = N->getMemoryVT();
-  EVT LoMemVT, HiMemVT;
   bool HiIsEmpty = false;
-  std::tie(LoMemVT, HiMemVT) =
+  auto [LoMemVT, HiMemVT] =
       DAG.GetDependentSplitDestVTs(MemoryVT, DataLo.getValueType(), &HiIsEmpty);
 
   // Split EVL
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) = DAG.SplitEVL(EVL, Data.getValueType(), DL);
+  auto [EVLLo, EVLHi] = DAG.SplitEVL(EVL, Data.getValueType(), DL);
 
   SDValue Lo, Hi;
   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
       N->getPointerInfo(), MachineMemOperand::MOStore,
       MemoryLocation::UnknownSize, Alignment, N->getAAInfo(), N->getRanges());
 
   Lo = DAG.getStoreVP(Ch, DL, DataLo, Ptr, Offset, MaskLo, EVLLo, LoMemVT, MMO,
                       N->getAddressingMode(), N->isTruncatingStore(),
SDValue DAGTypeLegalizer::SplitVecOp_VP_STRIDED_STORE(VPStridedStoreSDNode *N,
 
   SDValue Data = N->getValue();
   SDValue LoData, HiData;
   if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
     GetSplitVector(Data, LoData, HiData);
   else
     std::tie(LoData, HiData) = DAG.SplitVector(Data, DL);
 
-  EVT LoMemVT, HiMemVT;
   bool HiIsEmpty = false;
-  std::tie(LoMemVT, HiMemVT) = DAG.GetDependentSplitDestVTs(
+  auto [LoMemVT, HiMemVT] = DAG.GetDependentSplitDestVTs(
       N->getMemoryVT(), LoData.getValueType(), &HiIsEmpty);
 
   SDValue Mask = N->getMask();
   SDValue LoMask, HiMask;
   if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC)
     SplitVecRes_SETCC(Mask.getNode(), LoMask, HiMask);
   else if (getTypeAction(Mask.getValueType()) ==
            TargetLowering::TypeSplitVector)
     GetSplitVector(Mask, LoMask, HiMask);
   else
     std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
 
-  SDValue LoEVL, HiEVL;
-  std::tie(LoEVL, HiEVL) =
+  auto [LoEVL, HiEVL] =
       DAG.SplitEVL(N->getVectorLength(), Data.getValueType(), DL);
 
   // Generate the low vp_strided_store
   SDValue Lo = DAG.getStridedStoreVP(
       N->getChain(), DL, LoData, N->getBasePtr(), N->getOffset(),
       N->getStride(), LoMask, LoEVL, LoMemVT, N->getMemOperand(),
       N->getAddressingMode(), N->isTruncatingStore(), N->isCompressingStore());
 
SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
   } else {
     if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
       GetSplitVector(Mask, MaskLo, MaskHi);
     else
       std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
   }
 
   EVT MemoryVT = N->getMemoryVT();
-  EVT LoMemVT, HiMemVT;
   bool HiIsEmpty = false;
-  std::tie(LoMemVT, HiMemVT) =
+  auto [LoMemVT, HiMemVT] =
       DAG.GetDependentSplitDestVTs(MemoryVT, DataLo.getValueType(), &HiIsEmpty);
 
   SDValue Lo, Hi, Res;
   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
       N->getPointerInfo(), MachineMemOperand::MOStore,
       MemoryLocation::UnknownSize, Alignment, N->getAAInfo(), N->getRanges());
 
   Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, Offset, MaskLo, LoMemVT, MMO,
if (auto *MSC = dyn_cast<MaskedScatterSDNode>(N)) {
               MSC->getValue()};
     }
     auto *VPSC = cast<VPScatterSDNode>(N);
     return {VPSC->getMask(), VPSC->getIndex(), VPSC->getScale(),
             VPSC->getValue()};
   }();
   // Split all operands
 
-  EVT LoMemVT, HiMemVT;
-  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
+  auto [LoMemVT, HiMemVT] = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue DataLo, DataHi;
   if (getTypeAction(Ops.Data.getValueType()) == TargetLowering::TypeSplitVector)
     // Split Data operand
     GetSplitVector(Ops.Data, DataLo, DataHi);
   else
     std::tie(DataLo, DataHi) = DAG.SplitVector(Ops.Data, DL);
 
if (auto *MSC = dyn_cast<MaskedScatterSDNode>(N)) {
     // part comes after the "Lo". So these two operations should be chained one
     // after another.
     SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi, Ops.Scale};
     return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), HiMemVT, DL, OpsHi,
                                 MMO, MSC->getIndexType(),
                                 MSC->isTruncatingStore());
   }
   auto *VPSC = cast<VPScatterSDNode>(N);
-  SDValue EVLLo, EVLHi;
-  std::tie(EVLLo, EVLHi) =
+  auto [EVLLo, EVLHi] =
       DAG.SplitEVL(VPSC->getVectorLength(), Ops.Data.getValueType(), DL);
 
   SDValue OpsLo[] = {Ch, DataLo, Ptr, IndexLo, Ops.Scale, MaskLo, EVLLo};
   Lo = DAG.getScatterVP(DAG.getVTList(MVT::Other), LoMemVT, DL, OpsLo, MMO,
                         VPSC->getIndexType());
 
   // The order of the Scatter operation after split is well defined. The "Hi"
   // part comes after the "Lo". So these two operations should be chained one
SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
   SDValue Ptr = N->getBasePtr();
   EVT MemoryVT = N->getMemoryVT();
   Align Alignment = N->getOriginalAlign();
   MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
   AAMDNodes AAInfo = N->getAAInfo();
   SDValue Lo, Hi;
   GetSplitVector(N->getOperand(1), Lo, Hi);
 
-  EVT LoMemVT, HiMemVT;
-  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
+  auto [LoMemVT, HiMemVT] = DAG.GetSplitDestVTs(MemoryVT);
 
   // Scalarize if the split halves are not byte-sized.
   if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized())
     return TLI.scalarizeVectorStore(N, DAG);
 
   if (isTruncating)
     Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
                            Alignment, MMOFlags, AAInfo);
SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
   EVT OutVT = N->getValueType(0);
   ElementCount NumElements = OutVT.getVectorElementCount();
   bool IsFloat = OutVT.isFloatingPoint();
 
   unsigned InElementSize = InVT.getScalarSizeInBits();
   unsigned OutElementSize = OutVT.getScalarSizeInBits();
 
   // Determine the split output VT. If its legal we can just split dirctly.
-  EVT LoOutVT, HiOutVT;
-  std::tie(LoOutVT, HiOutVT) = DAG.GetSplitDestVTs(OutVT);
+  auto [LoOutVT, HiOutVT] = DAG.GetSplitDestVTs(OutVT);
   assert(LoOutVT == HiOutVT && "Unequal split?");
 
   // If the input elements are only 1/2 the width of the result elements,
   // just use the normal splitting. Our trick only work if there's room
   // to split more than once.
   if (isTypeLegal(LoOutVT) ||
       InElementSize <= OutElementSize * 2)
     return SplitVecOp_UnaryOp(N);
SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
   EVT PartResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt);
   EVT WideResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt*2);
 
   if (N->getOpcode() == ISD::SETCC) {
     LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
     HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
   } else {
     assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
-    SDValue MaskLo, MaskHi, EVLLo, EVLHi;
-    std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
-    std::tie(EVLLo, EVLHi) =
+    auto [MaskLo, MaskHi] = SplitMask(N->getOperand(3));
+    auto [EVLLo, EVLHi] =
         DAG.SplitEVL(N->getOperand(4), N->getValueType(0), DL);
     LoRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Lo0, Lo1,
                         N->getOperand(2), MaskLo, EVLLo);
     HiRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Hi0, Hi1,
                         N->getOperand(2), MaskHi, EVLHi);
   }
   SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
 
if (N->isStrictFPOpcode()) {
     Hi = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other }, 
                      { N->getOperand(0), Hi, N->getOperand(2) });
     // Legalize the chain result - switch anything that used the old chain to
     // use the new one.
     SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 
                                    Lo.getValue(1), Hi.getValue(1));
     ReplaceValueWith(SDValue(N, 1), NewChain);
   } else if (N->getOpcode() == ISD::VP_FP_ROUND) {
-    SDValue MaskLo, MaskHi, EVLLo, EVLHi;
-    std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
-    std::tie(EVLLo, EVLHi) =
+    auto [MaskLo, MaskHi] = SplitMask(N->getOperand(1));
+    auto [EVLLo, EVLHi] =
         DAG.SplitEVL(N->getOperand(2), N->getValueType(0), DL);
     Lo = DAG.getNode(ISD::VP_FP_ROUND, DL, OutVT, Lo, MaskLo, EVLLo);
     Hi = DAG.getNode(ISD::VP_FP_ROUND, DL, OutVT, Hi, MaskHi, EVLHi);
   } else {
     Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
     Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
   }
 
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
   // The result (and the first input) has a legal vector type, but the second
   // input needs splitting.
 
   SDLoc DL(N);
 
-  EVT LHSLoVT, LHSHiVT;
-  std::tie(LHSLoVT, LHSHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  auto [LHSLoVT, LHSHiVT] = DAG.GetSplitDestVTs(N->getValueType(0));
 
   if (!isTypeLegal(LHSLoVT) || !isTypeLegal(LHSHiVT))
     return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
 
-  SDValue LHSLo, LHSHi;
-  std::tie(LHSLo, LHSHi) =
-      DAG.SplitVector(N->getOperand(0), DL, LHSLoVT, LHSHiVT);
+  auto [LHSLo, LHSHi] = DAG.SplitVector(N->getOperand(0), DL, LHSLoVT, LHSHiVT);
 
-  SDValue RHSLo, RHSHi;
-  std::tie(RHSLo, RHSHi) = DAG.SplitVector(N->getOperand(1), DL);
+  auto [RHSLo, RHSHi] = DAG.SplitVector(N->getOperand(1), DL);
 
   SDValue Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLoVT, LHSLo, RHSLo);
   SDValue Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHiVT, LHSHi, RHSHi);
 
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Lo, Hi);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_FP_TO_XINT_SAT(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
 
   // A vector must always be stored in memory as-is, i.e. without any padding
   // between the elements, since various code depend on it, e.g. in the
   // handling of a bitcast of a vector type to int, which may be done with a
   // vector store followed by an integer load. A vector that does not have
   // elements that are byte-sized must therefore be stored as an integer
   // built out of the extracted vector elements.
   if (!LD->getMemoryVT().isByteSized()) {
-    SDValue Value, NewChain;
-    std::tie(Value, NewChain) = TLI.scalarizeVectorLoad(LD, DAG);
+    auto [Value, NewChain] = TLI.scalarizeVectorLoad(LD, DAG);
     ReplaceValueWith(SDValue(LD, 0), Value);
     ReplaceValueWith(SDValue(LD, 1), NewChain);
     return SDValue();
   }
 
   SDValue Result;
   SmallVector<SDValue, 16> LdChain;  // Chain for the series of load
   if (ExtType != ISD::NON_EXTLOAD)