[LoongArch] Lower BlockAddress/JumpTable

[wangleiat]

Summary

This patch uses a unified interface for lower GlobalAddress ConstantPool
BlockAddress and JumpTable.

This patch allows lowering addresses by using PC-relative addressing
for DSO-local symbols, and accessing the address through the global
offset table for DSO-preemptable symbols.

Remove hardcoded MininumJumpTableEntries for test lower JumpTable.

Also updated some test cases using ConstantPool, due to the addition of
relocation information.

[xen0n]

This mostly looks okay, thanks! I'd wait for more people to have a look at this though. We're very close to passing ninja check with native builds with this.

llvm/lib/Target/LoongArch/CMakeLists.txt

 tablegen(LLVM LoongArchGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM LoongArchGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(LoongArchCommonTableGen)
 
 add_llvm_target(LoongArchCodeGen
   LoongArchAsmPrinter.cpp
   LoongArchExpandAtomicPseudoInsts.cpp
+  LoongArchExpandPseudoInsts.cpp
   LoongArchFrameLowering.cpp
   LoongArchInstrInfo.cpp
   LoongArchISelDAGToDAG.cpp
   LoongArchISelLowering.cpp
   LoongArchMCInstLower.cpp
   LoongArchRegisterInfo.cpp
   LoongArchSubtarget.cpp
   LoongArchTargetMachine.cpp

llvm/lib/Target/LoongArch/LoongArch.h

bool lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                         AsmPrinter &AP);
 bool lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO,
                                              MCOperand &MCOp,
                                              const AsmPrinter &AP);
 
 FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
 FunctionPass *createLoongArchExpandAtomicPseudoPass();
 void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
+
+FunctionPass *createLoongArchPreRAExpandPseudoPass();
+void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &);
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCH_H

llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp

+//===-- LoongArchExpandPseudoInsts.cpp - Expand pseudo instructions -------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a pass that expands pseudo instructions into target
+// instructions.
+//
+//===----------------------------------------------------------------------===//
+
+#include "LoongArch.h"
+#include "LoongArchInstrInfo.h"
+#include "LoongArchTargetMachine.h"
+#include "MCTargetDesc/LoongArchBaseInfo.h"
+#include "MCTargetDesc/LoongArchMCTargetDesc.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/MC/MCContext.h"
+
+using namespace llvm;
+
+#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME                                     \
+  "LoongArch Pre-RA pseudo instruction expansion pass"
+
+namespace {
+
+class LoongArchPreRAExpandPseudo : public MachineFunctionPass {
+public:
+  const LoongArchInstrInfo *TII;
+  static char ID;
+
+  LoongArchPreRAExpandPseudo() : MachineFunctionPass(ID) {
+    initializeLoongArchPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+  StringRef getPassName() const override {
+    return LOONGARCH_PRERA_EXPAND_PSEUDO_NAME;
+  }
+
+private:
+  bool expandMBB(MachineBasicBlock &MBB);
+  bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+                MachineBasicBlock::iterator &NextMBBI);
+  bool expandPcalau12iInstPair(MachineBasicBlock &MBB,
+                               MachineBasicBlock::iterator MBBI,
+                               MachineBasicBlock::iterator &NextMBBI,
+                               unsigned FlagsHi, unsigned SecondOpcode,
+                               unsigned FlagsLo);
+  bool expandLoadAddressPcrel(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI,
+                              MachineBasicBlock::iterator &NextMBBI);
+  bool expandLoadAddressGot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            MachineBasicBlock::iterator &NextMBBI);
+};
+
+char LoongArchPreRAExpandPseudo::ID = 0;
+
+bool LoongArchPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+  TII =
+      static_cast<const LoongArchInstrInfo *>(MF.getSubtarget().getInstrInfo());
+  bool Modified = false;
+  for (auto &MBB : MF)
+    Modified |= expandMBB(MBB);
+  return Modified;
+}
+
+bool LoongArchPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
+  bool Modified = false;
+
+  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+  while (MBBI != E) {
+    MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+    Modified |= expandMI(MBB, MBBI, NMBBI);
+    MBBI = NMBBI;
+  }
+
+  return Modified;
+}
+
+bool LoongArchPreRAExpandPseudo::expandMI(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI) {
+  switch (MBBI->getOpcode()) {
+  case LoongArch::PseudoLA_PCREL:
+    return expandLoadAddressPcrel(MBB, MBBI, NextMBBI);
+  case LoongArch::PseudoLA_GOT:
+    return expandLoadAddressGot(MBB, MBBI, NextMBBI);
+  }
+  return false;
+}
+
+bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
+    unsigned SecondOpcode, unsigned FlagsLo) {
+  MachineFunction *MF = MBB.getParent();
+  MachineInstr &MI = *MBBI;
+  DebugLoc DL = MI.getDebugLoc();
+
+  Register DestReg = MI.getOperand(0).getReg();
+  Register ScratchReg =
+      MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
+  MachineOperand &Symbol = MI.getOperand(1);
+
+  BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
+      .addDisp(Symbol, 0, FlagsHi);
+
+  MachineInstr *SecondMI =
+      BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
+          .addReg(ScratchReg)
+          .addDisp(Symbol, 0, FlagsLo);
+
+  if (MI.hasOneMemOperand())
+    SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
+
+  MI.eraseFromParent();
+  return true;
+}
+
+bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI) {
+  MachineFunction *MF = MBB.getParent();
+  const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
+  unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
+  return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_PCREL_HI,
+                                 SecondOpcode, LoongArchII::MO_PCREL_LO);
+}
+
+bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI) {
+  MachineFunction *MF = MBB.getParent();
+  const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
+  unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
+  return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_GOT_PC_HI,
+                                 SecondOpcode, LoongArchII::MO_GOT_PC_LO);
+}
+
+} // end namespace
+
+INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "LoongArch-prera-expand-pseudo",
+                LOONGARCH_PRERA_EXPAND_PSEUDO_NAME, false, false)
+
+namespace llvm {
+
+FunctionPass *createLoongArchPreRAExpandPseudoPass() {
+  return new LoongArchPreRAExpandPseudo();
+}
+
+} // end namespace llvm

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
                         LoongArchCCAssignFn Fn) const;
   void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
                          const SmallVectorImpl<ISD::OutputArg> &Outs,
                          bool IsRet, CallLoweringInfo *CLI,
                          LoongArchCCAssignFn Fn) const;
 
+  template <class NodeTy>
+  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
 
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
   // TODO: add necessary setOperationAction calls later.
   setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom);
   setOperationAction(ISD::ROTL, GRLenVT, Expand);
   setOperationAction(ISD::CTPOP, GRLenVT, Expand);
 
-  setOperationAction({ISD::GlobalAddress, ISD::ConstantPool}, GRLenVT, Custom);
+  setOperationAction({ISD::GlobalAddress, ISD::BlockAddress, ISD::ConstantPool,
+                      ISD::JumpTable},
+                     GRLenVT, Custom);
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
   setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
   if (Subtarget.is64Bit())
     setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
 
   setOperationAction(ISD::DYNAMIC_STACKALLOC, GRLenVT, Expand);
if (Subtarget.hasBasicD()) {
     setOperationAction(ISD::BR_CC, MVT::f64, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
     setOperationAction(ISD::FMA, MVT::f64, Legal);
     setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
     setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
   }
 
-  // Effectively disable jump table generation.
-  setMinimumJumpTableEntries(INT_MAX);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
 
   setOperationAction(ISD::BR_CC, GRLenVT, Expand);
   setOperationAction(ISD::SELECT_CC, GRLenVT, Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, GRLenVT, Expand);
   if (!Subtarget.is64Bit())
     setLibcallName(RTLIB::MUL_I128, nullptr);
SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
                                                 SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   case ISD::EH_DWARF_CFA:
     return lowerEH_DWARF_CFA(Op, DAG);
   case ISD::GlobalAddress:
     return lowerGlobalAddress(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN:
     return lowerINTRINSIC_WO_CHAIN(Op, DAG);
+  case ISD::BlockAddress:
+    return lowerBlockAddress(Op, DAG);
+  case ISD::JumpTable:
+    return lowerJumpTable(Op, DAG);
   case ISD::SHL_PARTS:
     return lowerShiftLeftParts(Op, DAG);
   case ISD::SRA_PARTS:
     return lowerShiftRightParts(Op, DAG, true);
   case ISD::SRL_PARTS:
     return lowerShiftRightParts(Op, DAG, false);
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
if (Op.getValueSizeInBits() > 32 && Subtarget.hasBasicF() &&
     return DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, MVT::i64, Dst);
   }
 
   EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
   SDValue Trunc = DAG.getNode(LoongArchISD::FTINT, DL, FPTy, Op.getOperand(0));
   return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc);
 }
 
-SDValue LoongArchTargetLowering::lowerConstantPool(SDValue Op,
-                                                   SelectionDAG &DAG) const {
-  SDLoc DL(Op);
-  EVT Ty = Op.getValueType();
-  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
+static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
+                             SelectionDAG &DAG, unsigned Flags) {
+  return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
+}
 
-  // FIXME: Only support PC-relative addressing to access the symbol.
-  // Target flags will be added later.
-  if (!isPositionIndependent()) {
-    SDValue ConstantN = DAG.getTargetConstantPool(
-        N->getConstVal(), Ty, N->getAlign(), N->getOffset());
-    SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, ConstantN),
-                   0);
-    SDValue Addr(DAG.getMachineNode(Subtarget.is64Bit() ? LoongArch::ADDI_D
-                                                        : LoongArch::ADDI_W,
-                                    DL, Ty, AddrHi, ConstantN),
-                 0);
-    return Addr;
-  }
-  report_fatal_error("Unable to lower ConstantPool");
+static SDValue getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty,
+                             SelectionDAG &DAG, unsigned Flags) {
+  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
+                                   Flags);
+
+static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
+                             SelectionDAG &DAG, unsigned Flags) {
+  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
+                                   N->getOffset(), Flags);
 }
 
-SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op,
-                                                    SelectionDAG &DAG) const {
-  SDLoc DL(Op);
+static SDValue getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
+                             SelectionDAG &DAG, unsigned Flags) {
+  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
+}
+
+template <class NodeTy>
+SDValue LoongArchTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
+                                         bool IsLocal) const {
+  SDLoc DL(N);
   EVT Ty = getPointerTy(DAG.getDataLayout());
-  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
-  unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
+  SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
+  // TODO: Check CodeModel.
+  if (IsLocal)
+    // This generates the pattern (PseudoLA_PCREL sym), which expands to
+    // (addi.w/d (pcalau12i %pc_hi20(sym)) %pc_lo12(sym)).
+    return SDValue(DAG.getMachineNode(LoongArch::PseudoLA_PCREL, DL, Ty, Addr),
+                   0);
 
-  // TODO: Support dso_preemptable and target flags.
-  if (GV->isDSOLocal()) {
-    SDValue GAHi =
-        DAG.getTargetGlobalAddress(GV, DL, Ty, 0, LoongArchII::MO_PCREL_HI);
-    SDValue GALo =
-        DAG.getTargetGlobalAddress(GV, DL, Ty, 0, LoongArchII::MO_PCREL_LO);
-    SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, GAHi), 0);
+  // This generates the pattern (PseudoLA_GOT sym), which expands to (ld.w/d
+  // (pcalau12i %got_pc_hi20(sym)) %got_pc_lo12(sym)).
+  return SDValue(DAG.getMachineNode(LoongArch::PseudoLA_GOT, DL, Ty, Addr), 0);
+}
 
-    return SDValue(DAG.getMachineNode(ADDIOp, DL, Ty, AddrHi, GALo), 0);
-  }
-  report_fatal_error("Unable to lowerGlobalAddress");
+SDValue LoongArchTargetLowering::lowerBlockAddress(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  return getAddr(cast<BlockAddressSDNode>(Op), DAG);
+
+SDValue LoongArchTargetLowering::lowerJumpTable(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  return getAddr(cast<JumpTableSDNode>(Op), DAG);
+}
+
+SDValue LoongArchTargetLowering::lowerConstantPool(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  return getAddr(cast<ConstantPoolSDNode>(Op), DAG);
+}
+
+SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op,
+                                                    SelectionDAG &DAG) const {
+  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
+  assert(N->getOffset() == 0 && "unexpected offset in global node");
+  return getAddr(N, DAG, N->getGlobal()->isDSOLocal());
 }
 
 SDValue LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                          SelectionDAG &DAG) const {
   unsigned IntNo = Op.getConstantOperandVal(0);
 
   switch (IntNo) {
   default:

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rj),
                                 [(loongarch_call GPR:$rj)]>,
                          PseudoInstExpansion<(JIRL R1, GPR:$rj, 0)>;
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in
 def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
                 PseudoInstExpansion<(JIRL R0, R1, 0)>;
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def PseudoLA_PCREL : Pseudo<(outs GPR:$dst), (ins grlenimm:$src), []>;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def PseudoLA_GOT : Pseudo<(outs GPR:$dst), (ins grlenimm:$src), []>;
+
 /// BSTRINS and BSTRPICK
 
 let Predicates = [IsLA32] in {
 def : Pat<(loongarch_bstrins GPR:$rd, GPR:$rj, uimm5:$msbd, uimm5:$lsbd),
           (BSTRINS_W GPR:$rd, GPR:$rj, uimm5:$msbd, uimm5:$lsbd)>;
 def : Pat<(loongarch_bstrpick GPR:$rj, uimm5:$msbd, uimm5:$lsbd),
           (BSTRPICK_W GPR:$rj, uimm5:$msbd, uimm5:$lsbd)>;
 } // Predicates = [IsLA32]

llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp

case LoongArchII::MO_CALL_PLT:
     Kind = LoongArchMCExpr::VK_LoongArch_CALL_PLT;
     break;
   case LoongArchII::MO_PCREL_HI:
     Kind = LoongArchMCExpr::VK_LoongArch_PCALA_HI20;
     break;
   case LoongArchII::MO_PCREL_LO:
     Kind = LoongArchMCExpr::VK_LoongArch_PCALA_LO12;
     break;
+  case LoongArchII::MO_GOT_PC_HI:
+    Kind = LoongArchMCExpr::VK_LoongArch_GOT_HI20;
+    break;
+  case LoongArchII::MO_GOT_PC_LO:
+    Kind = LoongArchMCExpr::VK_LoongArch_GOT_LO12;
+    break;
     // TODO: Handle more target-flags.
   }
 
   const MCExpr *ME =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
     ME = MCBinaryExpr::createAdd(
case MachineOperand::MO_GlobalAddress:
     break;
   case MachineOperand::MO_MachineBasicBlock:
     MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
     break;
   case MachineOperand::MO_ExternalSymbol:
     MCOp = lowerSymbolOperand(
         MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
     break;
-  // TODO: lower special operands
   case MachineOperand::MO_BlockAddress:
+    MCOp = lowerSymbolOperand(
+        MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
+    break;
   case MachineOperand::MO_JumpTableIndex:
+    MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
     break;
   }
   return true;
 }
 
 bool llvm::lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI,
                                               MCInst &OutMI, AsmPrinter &AP) {
   OutMI.setOpcode(MI->getOpcode());
 
   for (const MachineOperand &MO : MI->operands()) {
     MCOperand MCOp;
     if (lowerLoongArchMachineOperandToMCOperand(MO, MCOp, AP))
       OutMI.addOperand(MCOp);
   }
   return false;
 }

llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "loongarch"
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget() {
   // Register the target.
   RegisterTargetMachine<LoongArchTargetMachine> X(getTheLoongArch32Target());
   RegisterTargetMachine<LoongArchTargetMachine> Y(getTheLoongArch64Target());
+  auto *PR = PassRegistry::getPassRegistry();
+  initializeLoongArchPreRAExpandPseudoPass(*PR);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit())
     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   assert(TT.isArch32Bit() && "only LA32 and LA64 are currently supported");
   return "e-m:e-p:32:32-i64:64-n32-S128";
 }
public:
 
   LoongArchTargetMachine &getLoongArchTargetMachine() const {
     return getTM<LoongArchTargetMachine>();
   }
 
   void addIRPasses() override;
   bool addInstSelector() override;
   void addPreEmitPass2() override;
+  void addPreRegAlloc() override;
 };
 } // end namespace
 
 TargetPassConfig *
 LoongArchTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new LoongArchPassConfig(*this, PM);
 }
 

 }
 
 void LoongArchPassConfig::addPreEmitPass2() {
   // Schedule the expansion of AtomicPseudos at the last possible moment,
   // avoiding the possibility for other passes to break the requirements for
   // forward progress in the LL/SC block.
   addPass(createLoongArchExpandAtomicPseudoPass());
 }
+
+void LoongArchPassConfig::addPreRegAlloc() {
+  addPass(createLoongArchPreRAExpandPseudoPass());
+}

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h

 // tracks.
 namespace LoongArchII {
 enum {
   MO_None,
   MO_CALL,
   MO_CALL_PLT,
   MO_PCREL_HI,
   MO_PCREL_LO,
+  MO_GOT_PC_HI,
+  MO_GOT_PC_LO,
   // TODO: Add more flags.
 };
 } // end namespace LoongArchII
 
 namespace LoongArchABI {
 enum ABI {
   ABI_ILP32S,
   ABI_ILP32F,

llvm/test/CodeGen/LoongArch/block-address.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+@addr = dso_local global ptr null
+
+define void @test_blockaddress() nounwind {
+; LA32-LABEL: test_blockaddress:
+; LA32:       # %bb.0:
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(addr)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(addr)
+; LA32-NEXT:    pcalau12i $a1, %pc_hi20(.Ltmp0)
+; LA32-NEXT:    addi.w $a1, $a1, %pc_lo12(.Ltmp0)
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    jr $a0
+; LA32-NEXT:  .Ltmp0: # Block address taken
+; LA32-NEXT:  .LBB0_1: # %block
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: test_blockaddress:
+; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a0, %pc_hi20(addr)
+; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(addr)
+; LA64-NEXT:    pcalau12i $a1, %pc_hi20(.Ltmp0)
+; LA64-NEXT:    addi.d $a1, $a1, %pc_lo12(.Ltmp0)
+; LA64-NEXT:    st.d $a1, $a0, 0
+; LA64-NEXT:    ld.d $a0, $a0, 0
+; LA64-NEXT:    jr $a0
+; LA64-NEXT:  .Ltmp0: # Block address taken
+; LA64-NEXT:  .LBB0_1: # %block
+; LA64-NEXT:    ret
+  store volatile ptr blockaddress(@test_blockaddress, %block), ptr @addr
+  %val = load volatile ptr, ptr @addr
+  indirectbr ptr %val, [label %block]
+
+block:
+  ret void
+}

llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll

; CHECK-NEXT:    ret
   ret i64 %1
 }
 
 define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
 ; CHECK-LABEL: caller_double_in_gpr_exhausted_fprs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT:    pcalau12i $a0, .LCPI21_0
-; CHECK-NEXT:    addi.d $a0, $a0, .LCPI21_0
-; CHECK-NEXT:    pcalau12i $a1, .LCPI21_1
-; CHECK-NEXT:    addi.d $a1, $a1, .LCPI21_1
-; CHECK-NEXT:    pcalau12i $a2, .LCPI21_2
-; CHECK-NEXT:    addi.d $a2, $a2, .LCPI21_2
-; CHECK-NEXT:    pcalau12i $a3, .LCPI21_3
-; CHECK-NEXT:    addi.d $a3, $a3, .LCPI21_3
-; CHECK-NEXT:    pcalau12i $a4, .LCPI21_4
-; CHECK-NEXT:    addi.d $a4, $a4, .LCPI21_4
-; CHECK-NEXT:    pcalau12i $a5, .LCPI21_5
-; CHECK-NEXT:    addi.d $a5, $a5, .LCPI21_5
-; CHECK-NEXT:    addi.d $a6, $zero, 1
-; CHECK-NEXT:    movgr2fr.d $fa0, $a6
-; CHECK-NEXT:    ffint.d.l $fa0, $fa0
-; CHECK-NEXT:    fld.d $fa1, $a5, 0
-; CHECK-NEXT:    fld.d $fa2, $a4, 0
-; CHECK-NEXT:    fld.d $fa3, $a3, 0
-; CHECK-NEXT:    fld.d $fa4, $a2, 0
-; CHECK-NEXT:    fld.d $fa5, $a1, 0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_0)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_0)
+; CHECK-NEXT:    fld.d $fa1, $a0, 0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_1)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_1)
+; CHECK-NEXT:    fld.d $fa2, $a0, 0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_2)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_2)
+; CHECK-NEXT:    fld.d $fa3, $a0, 0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_3)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_3)
+; CHECK-NEXT:    fld.d $fa4, $a0, 0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_4)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_4)
+; CHECK-NEXT:    fld.d $fa5, $a0, 0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_5)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_5)
 ; CHECK-NEXT:    fld.d $fa6, $a0, 0
-; CHECK-NEXT:    pcalau12i $a0, .LCPI21_6
-; CHECK-NEXT:    addi.d $a0, $a0, .LCPI21_6
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI21_6)
+; CHECK-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI21_6)
 ; CHECK-NEXT:    fld.d $fa7, $a0, 0
+; CHECK-NEXT:    addi.d $a0, $zero, 1
+; CHECK-NEXT:    movgr2fr.d $fa0, $a0
+; CHECK-NEXT:    ffint.d.l $fa0, $fa0
 ; CHECK-NEXT:    ori $a0, $zero, 0
 ; CHECK-NEXT:    lu32i.d $a0, 131072
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 1026
 ; CHECK-NEXT:    bl %plt(callee_double_in_gpr_exhausted_fprs)
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_double_in_gpr_exhausted_fprs(

llvm/test/CodeGen/LoongArch/double-imm.ll

 ; LA64-NEXT:    fneg.d $fa0, $fa0
 ; LA64-NEXT:    ret
   ret double -0.0
 }
 
 define double @f64_constant_pi() nounwind {
 ; LA32-LABEL: f64_constant_pi:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    pcalau12i $a0, .LCPI2_0
-; LA32-NEXT:    addi.w $a0, $a0, .LCPI2_0
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI2_0)
 ; LA32-NEXT:    fld.d $fa0, $a0, 0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_constant_pi:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    pcalau12i $a0, .LCPI2_0
-; LA64-NEXT:    addi.d $a0, $a0, .LCPI2_0
+; LA64-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI2_0)
 ; LA64-NEXT:    fld.d $fa0, $a0, 0
 ; LA64-NEXT:    ret
   ret double 3.1415926535897931159979634685441851615905761718750
 }
 
 define double @f64_add_fimm1(double %a) nounwind {
 ; LA32-LABEL: f64_add_fimm1:
 ; LA32:       # %bb.0:

llvm/test/CodeGen/LoongArch/float-imm.ll

 ; LA64-NEXT:    fneg.s $fa0, $fa0
 ; LA64-NEXT:    ret
   ret float -0.0
 }
 
 define float @f32_constant_pi() nounwind {
 ; LA32-LABEL: f32_constant_pi:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    pcalau12i $a0, .LCPI2_0
-; LA32-NEXT:    addi.w $a0, $a0, .LCPI2_0
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI2_0)
 ; LA32-NEXT:    fld.s $fa0, $a0, 0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_constant_pi:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    pcalau12i $a0, .LCPI2_0
-; LA64-NEXT:    addi.d $a0, $a0, .LCPI2_0
+; LA64-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI2_0)
 ; LA64-NEXT:    fld.s $fa0, $a0, 0
 ; LA64-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @f32_add_fimm1(float %a) nounwind {
 ; LA32-LABEL: f32_add_fimm1:
 ; LA32:       # %bb.0:

llvm/test/CodeGen/LoongArch/global-address.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --relocation-model=static < %s | FileCheck %s --check-prefix=LA32NOPIC
+; RUN: llc --mtriple=loongarch32 --relocation-model=pic < %s | FileCheck %s --check-prefix=LA32PIC
+; RUN: llc --mtriple=loongarch64 --relocation-model=static < %s | FileCheck %s --check-prefix=LA64NOPIC
+; RUN: llc --mtriple=loongarch64 --relocation-model=pic < %s | FileCheck %s --check-prefix=LA64PIC
+
+@g = dso_local global i32 zeroinitializer, align 4
+@G = global i32 zeroinitializer, align 4
+
+define void @foo() nounwind {
+; LA32NOPIC-LABEL: foo:
+; LA32NOPIC:       # %bb.0:
+; LA32NOPIC-NEXT:    pcalau12i $a0, %got_hi20(G)
+; LA32NOPIC-NEXT:    ld.w $a0, $a0, %got_lo12(G)
+; LA32NOPIC-NEXT:    ld.w $a0, $a0, 0
+; LA32NOPIC-NEXT:    pcalau12i $a0, %pc_hi20(g)
+; LA32NOPIC-NEXT:    addi.w $a0, $a0, %pc_lo12(g)
+; LA32NOPIC-NEXT:    ld.w $a0, $a0, 0
+; LA32NOPIC-NEXT:    ret
+;
+; LA32PIC-LABEL: foo:
+; LA32PIC:       # %bb.0:
+; LA32PIC-NEXT:    pcalau12i $a0, %got_hi20(G)
+; LA32PIC-NEXT:    ld.w $a0, $a0, %got_lo12(G)
+; LA32PIC-NEXT:    ld.w $a0, $a0, 0
+; LA32PIC-NEXT:    pcalau12i $a0, %pc_hi20(.Lg$local)
+; LA32PIC-NEXT:    addi.w $a0, $a0, %pc_lo12(.Lg$local)
+; LA32PIC-NEXT:    ld.w $a0, $a0, 0
+; LA32PIC-NEXT:    ret
+;
+; LA64NOPIC-LABEL: foo:
+; LA64NOPIC:       # %bb.0:
+; LA64NOPIC-NEXT:    pcalau12i $a0, %got_hi20(G)
+; LA64NOPIC-NEXT:    ld.d $a0, $a0, %got_lo12(G)
+; LA64NOPIC-NEXT:    ld.w $a0, $a0, 0
+; LA64NOPIC-NEXT:    pcalau12i $a0, %pc_hi20(g)
+; LA64NOPIC-NEXT:    addi.d $a0, $a0, %pc_lo12(g)
+; LA64NOPIC-NEXT:    ld.w $a0, $a0, 0
+; LA64NOPIC-NEXT:    ret
+;
+; LA64PIC-LABEL: foo:
+; LA64PIC:       # %bb.0:
+; LA64PIC-NEXT:    pcalau12i $a0, %got_hi20(G)
+; LA64PIC-NEXT:    ld.d $a0, $a0, %got_lo12(G)
+; LA64PIC-NEXT:    ld.w $a0, $a0, 0
+; LA64PIC-NEXT:    pcalau12i $a0, %pc_hi20(.Lg$local)
+; LA64PIC-NEXT:    addi.d $a0, $a0, %pc_lo12(.Lg$local)
+; LA64PIC-NEXT:    ld.w $a0, $a0, 0
+; LA64PIC-NEXT:    ret
+  %V = load volatile i32, ptr @G
+  %v = load volatile i32, ptr @g
+  ret void
+}

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

 ; LA64-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
 
 define i32 @convert_double_to_u32(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_u32:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    pcalau12i $a0, .LCPI7_0
-; LA32-NEXT:    addi.w $a0, $a0, .LCPI7_0
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI7_0)
 ; LA32-NEXT:    fld.d $fa1, $a0, 0
 ; LA32-NEXT:    fsub.d $fa2, $fa0, $fa1
 ; LA32-NEXT:    ftintrz.w.d $fa2, $fa2
 ; LA32-NEXT:    movfr2gr.s $a0, $fa2
 ; LA32-NEXT:    lu12i.w $a1, -524288
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a1, $fcc0

 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl %plt(__fixunsdfdi)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_u64:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    pcalau12i $a0, .LCPI9_0
-; LA64-NEXT:    addi.d $a0, $a0, .LCPI9_0
+; LA64-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI9_0)
 ; LA64-NEXT:    fld.d $fa1, $a0, 0
 ; LA64-NEXT:    fsub.d $fa2, $fa0, $fa1
 ; LA64-NEXT:    ftintrz.l.d $fa2, $fa2
 ; LA64-NEXT:    movfr2gr.d $a0, $fa2
 ; LA64-NEXT:    lu52i.d $a1, $zero, -2048
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a1, $fcc0

 
 define double @convert_u32_to_double(i32 %a) nounwind {
 ; LA32-LABEL: convert_u32_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    lu12i.w $a1, 275200
 ; LA32-NEXT:    st.w $a1, $sp, 12
 ; LA32-NEXT:    st.w $a0, $sp, 8
-; LA32-NEXT:    pcalau12i $a0, .LCPI12_0
-; LA32-NEXT:    addi.w $a0, $a0, .LCPI12_0
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI12_0)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI12_0)
 ; LA32-NEXT:    fld.d $fa0, $a0, 0
 ; LA32-NEXT:    fld.d $fa1, $sp, 8
 ; LA32-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u32_to_double:
 ; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI12_0)
+; LA64-NEXT:    addi.d $a1, $a1, %pc_lo12(.LCPI12_0)
+; LA64-NEXT:    fld.d $fa0, $a1, 0
 ; LA64-NEXT:    lu52i.d $a1, $zero, 1107
-; LA64-NEXT:    movgr2fr.d $fa0, $a1
-; LA64-NEXT:    pcalau12i $a1, .LCPI12_0
-; LA64-NEXT:    addi.d $a1, $a1, .LCPI12_0
-; LA64-NEXT:    fld.d $fa1, $a1, 0
-; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
+; LA64-NEXT:    movgr2fr.d $fa1, $a1
+; LA64-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA64-NEXT:    lu12i.w $a1, 275200
 ; LA64-NEXT:    bstrins.d $a0, $a1, 63, 32
 ; LA64-NEXT:    movgr2fr.d $fa1, $a0
 ; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
 ; LA64-NEXT:    ret
   %1 = uitofp i32 %a to double
   ret double %1
 }

 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srli.d $a1, $a0, 32
 ; LA64-NEXT:    lu52i.d $a2, $zero, 1107
 ; LA64-NEXT:    or $a1, $a1, $a2
 ; LA64-NEXT:    movgr2fr.d $fa0, $a1
-; LA64-NEXT:    pcalau12i $a1, .LCPI13_0
-; LA64-NEXT:    addi.d $a1, $a1, .LCPI13_0
+; LA64-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI13_0)
+; LA64-NEXT:    addi.d $a1, $a1, %pc_lo12(.LCPI13_0)
 ; LA64-NEXT:    fld.d $fa1, $a1, 0
 ; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
 ; LA64-NEXT:    lu12i.w $a1, 275200
 ; LA64-NEXT:    bstrins.d $a0, $a1, 63, 32
 ; LA64-NEXT:    movgr2fr.d $fa1, $a0
 ; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
 ; LA64-NEXT:    ret
   %1 = uitofp i64 %a to double

llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll

 ; LA64D-NEXT:    ret
   %1 = fptoui float %a to i16
   ret i16 %1
 }
 
 define i32 @convert_float_to_u32(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_u32:
 ; LA32F:       # %bb.0:
-; LA32F-NEXT:    pcalau12i $a0, .LCPI6_0
-; LA32F-NEXT:    addi.w $a0, $a0, .LCPI6_0
+; LA32F-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; LA32F-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI6_0)
 ; LA32F-NEXT:    fld.s $fa1, $a0, 0
 ; LA32F-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA32F-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa2
 ; LA32F-NEXT:    lu12i.w $a1, -524288
 ; LA32F-NEXT:    xor $a0, $a0, $a1
 ; LA32F-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32F-NEXT:    movcf2gr $a1, $fcc0
 ; LA32F-NEXT:    masknez $a0, $a0, $a1
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA32F-NEXT:    maskeqz $a1, $a2, $a1
 ; LA32F-NEXT:    or $a0, $a1, $a0
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_u32:
 ; LA32D:       # %bb.0:
-; LA32D-NEXT:    pcalau12i $a0, .LCPI6_0
-; LA32D-NEXT:    addi.w $a0, $a0, .LCPI6_0
+; LA32D-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; LA32D-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI6_0)
 ; LA32D-NEXT:    fld.s $fa1, $a0, 0
 ; LA32D-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA32D-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa2
 ; LA32D-NEXT:    lu12i.w $a1, -524288
 ; LA32D-NEXT:    xor $a0, $a0, $a1
 ; LA32D-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32D-NEXT:    movcf2gr $a1, $fcc0
 ; LA32D-NEXT:    masknez $a0, $a0, $a1
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a2, $fa0
 ; LA32D-NEXT:    maskeqz $a1, $a2, $a1
 ; LA32D-NEXT:    or $a0, $a1, $a0
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u32:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    pcalau12i $a0, .LCPI6_0
-; LA64F-NEXT:    addi.d $a0, $a0, .LCPI6_0
+; LA64F-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; LA64F-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI6_0)
 ; LA64F-NEXT:    fld.s $fa1, $a0, 0
 ; LA64F-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA64F-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa2
 ; LA64F-NEXT:    lu12i.w $a1, -524288
 ; LA64F-NEXT:    xor $a0, $a0, $a1
 ; LA64F-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64F-NEXT:    movcf2gr $a1, $fcc0

 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl %plt(__fixunssfdi)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u64:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    pcalau12i $a0, .LCPI7_0
-; LA64F-NEXT:    addi.d $a0, $a0, .LCPI7_0
+; LA64F-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; LA64F-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI7_0)
 ; LA64F-NEXT:    fld.s $fa1, $a0, 0
 ; LA64F-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA64F-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa2
 ; LA64F-NEXT:    lu52i.d $a1, $zero, -2048
 ; LA64F-NEXT:    xor $a0, $a0, $a1
 ; LA64F-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64F-NEXT:    movcf2gr $a1, $fcc0
 ; LA64F-NEXT:    masknez $a0, $a0, $a1
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64F-NEXT:    maskeqz $a1, $a2, $a1
 ; LA64F-NEXT:    or $a0, $a1, $a0
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_u64:
 ; LA64D:       # %bb.0:
-; LA64D-NEXT:    pcalau12i $a0, .LCPI7_0
-; LA64D-NEXT:    addi.d $a0, $a0, .LCPI7_0
+; LA64D-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; LA64D-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI7_0)
 ; LA64D-NEXT:    fld.s $fa1, $a0, 0
 ; LA64D-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA64D-NEXT:    ftintrz.l.s $fa2, $fa2
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa2
 ; LA64D-NEXT:    lu52i.d $a1, $zero, -2048
 ; LA64D-NEXT:    xor $a0, $a0, $a1
 ; LA64D-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64D-NEXT:    movcf2gr $a1, $fcc0

 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_u32_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    lu12i.w $a1, 275200
 ; LA32D-NEXT:    st.w $a1, $sp, 12
 ; LA32D-NEXT:    st.w $a0, $sp, 8
-; LA32D-NEXT:    pcalau12i $a0, .LCPI14_0
-; LA32D-NEXT:    addi.w $a0, $a0, .LCPI14_0
+; LA32D-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI14_0)
+; LA32D-NEXT:    addi.w $a0, $a0, %pc_lo12(.LCPI14_0)
 ; LA32D-NEXT:    fld.d $fa0, $a0, 0
 ; LA32D-NEXT:    fld.d $fa1, $sp, 8
 ; LA32D-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32D-NEXT:    fcvt.s.d $fa0, $fa0
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u32_to_float:

llvm/test/CodeGen/LoongArch/jump-table.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s \
+; RUN: llc --mtriple=loongarch32 --min-jump-table-entries=5 < %s \
 ; RUN:   | FileCheck %s --check-prefix=LA32
-; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN: llc --mtriple=loongarch64 --min-jump-table-entries=5 < %s \
 ; RUN:   | FileCheck %s --check-prefix=LA64
+; RUN: llc --mtriple=loongarch32 --min-jump-table-entries=4 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32-JT
+; RUN: llc --mtriple=loongarch64 --min-jump-table-entries=4 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64-JT
+
+;; The default mininum number of entries to use a jump table is 4.
+;;
+;; Note: The parameter `--min-jump-table-entries` will have no effect once we
+;; have set the default value using `setMinimumJumpTableEntries`.
 
 define void @switch_4_arms(i32 %in, ptr %out) nounwind {
 ; LA32-LABEL: switch_4_arms:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a2, $zero, 2
 ; LA32-NEXT:    blt $a2, $a0, .LBB0_4
 ; LA32-NEXT:  # %bb.1: # %entry
 ; LA32-NEXT:    ori $a3, $zero, 1

 ; LA64-NEXT:  .LBB0_8: # %bb1
 ; LA64-NEXT:    ori $a0, $zero, 4
 ; LA64-NEXT:    st.w $a0, $a1, 0
 ; LA64-NEXT:    ret
 ; LA64-NEXT:  .LBB0_9: # %bb3
 ; LA64-NEXT:    st.w $a2, $a1, 0
 ; LA64-NEXT:  .LBB0_10: # %exit
 ; LA64-NEXT:    ret
+;
+; LA32-JT-LABEL: switch_4_arms:
+; LA32-JT:       # %bb.0: # %entry
+; LA32-JT-NEXT:    addi.w $a2, $a0, -1
+; LA32-JT-NEXT:    ori $a0, $zero, 3
+; LA32-JT-NEXT:    bltu $a0, $a2, .LBB0_6
+; LA32-JT-NEXT:  # %bb.1: # %entry
+; LA32-JT-NEXT:    pcalau12i $a3, %pc_hi20(.LJTI0_0)
+; LA32-JT-NEXT:    addi.w $a3, $a3, %pc_lo12(.LJTI0_0)
+; LA32-JT-NEXT:    alsl.w $a2, $a2, $a3, 2
+; LA32-JT-NEXT:    ld.w $a2, $a2, 0
+; LA32-JT-NEXT:    jr $a2
+; LA32-JT-NEXT:  .LBB0_2: # %bb1
+; LA32-JT-NEXT:    ori $a0, $zero, 4
+; LA32-JT-NEXT:    b .LBB0_5
+; LA32-JT-NEXT:  .LBB0_3: # %bb3
+; LA32-JT-NEXT:    ori $a0, $zero, 2
+; LA32-JT-NEXT:    b .LBB0_5
+; LA32-JT-NEXT:  .LBB0_4: # %bb4
+; LA32-JT-NEXT:    ori $a0, $zero, 1
+; LA32-JT-NEXT:  .LBB0_5: # %exit
+; LA32-JT-NEXT:    st.w $a0, $a1, 0
+; LA32-JT-NEXT:  .LBB0_6: # %exit
+; LA32-JT-NEXT:    ret
+;
+; LA64-JT-LABEL: switch_4_arms:
+; LA64-JT:       # %bb.0: # %entry
+; LA64-JT-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-JT-NEXT:    addi.d $a2, $a0, -1
+; LA64-JT-NEXT:    ori $a0, $zero, 3
+; LA64-JT-NEXT:    bltu $a0, $a2, .LBB0_6
+; LA64-JT-NEXT:  # %bb.1: # %entry
+; LA64-JT-NEXT:    slli.d $a2, $a2, 3
+; LA64-JT-NEXT:    pcalau12i $a3, %pc_hi20(.LJTI0_0)
+; LA64-JT-NEXT:    addi.d $a3, $a3, %pc_lo12(.LJTI0_0)
+; LA64-JT-NEXT:    ldx.d $a2, $a2, $a3
+; LA64-JT-NEXT:    jr $a2
+; LA64-JT-NEXT:  .LBB0_2: # %bb1
+; LA64-JT-NEXT:    ori $a0, $zero, 4
+; LA64-JT-NEXT:    b .LBB0_5
+; LA64-JT-NEXT:  .LBB0_3: # %bb3
+; LA64-JT-NEXT:    ori $a0, $zero, 2
+; LA64-JT-NEXT:    b .LBB0_5
+; LA64-JT-NEXT:  .LBB0_4: # %bb4
+; LA64-JT-NEXT:    ori $a0, $zero, 1
+; LA64-JT-NEXT:  .LBB0_5: # %exit
+; LA64-JT-NEXT:    st.w $a0, $a1, 0
+; LA64-JT-NEXT:  .LBB0_6: # %exit
+; LA64-JT-NEXT:    ret
 entry:
   switch i32 %in, label %exit [
     i32 1, label %bb1
     i32 2, label %bb2
     i32 3, label %bb3
     i32 4, label %bb4
   ]
 bb1: