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Differential D134273

[AArch64] Enable LSLFast for modern OoO cpus
ClosedPublic

Authored by dmgreen on Sep 20 2022, 3:22 AM.

Details

Reviewers
labrinea
samtebbs
david-arm
jaykang10
Summary

This patch enables the LSLFast feature for Cortex-A76, Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A710, Cortex-X1, Cortex-X2, Neoverse N1, Neoverse N2, Neoverse V1 and the Neoverse 512TB psuedo-cpu, in-line with the software optimization guides for those CPUs.

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > libFuzzer.libFuzzer::value-profile-load.test

Event Timeline

dmgreen created this revision.Sep 20 2022, 3:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 20 2022, 3:22 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
dmgreen requested review of this revision.Sep 20 2022, 3:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 20 2022, 3:22 AM
Harbormaster completed remote builds in B187723: Diff 461530.Sep 20 2022, 3:53 AM
samtebbs accepted this revision.Sep 20 2022, 6:05 AM

LGTM

This revision is now accepted and ready to land.Sep 20 2022, 6:05 AM
dmgreen mentioned this in rGcb375e8c1f39: [AArch64] Enable LSLFast for modern OoO cpus.Sep 20 2022, 9:09 AM
dmgreen closed this revision.Sep 20 2022, 9:11 AM

Thanks

Closed with https://reviews.llvm.org/rGcb375e8c1f39.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
44 lines
test/
CodeGen/
AArch64/
199 lines

Diff 461530

llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 711 Lines • ▼ Show 20 Linesdef TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
FeatureFuseAES]>; FeatureFuseAES]>;
def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
"Cortex-A75 ARM processors", [ "Cortex-A75 ARM processors", [
FeatureFuseAES]>; FeatureFuseAES]>;
def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
"Cortex-A76 ARM processors", [ "Cortex-A76 ARM processors", [
FeatureFuseAES]>; FeatureFuseAES,
FeatureLSLFast]>;
def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
"Cortex-A77 ARM processors", [ "Cortex-A77 ARM processors", [
FeatureCmpBccFusion, FeatureCmpBccFusion,
FeatureFuseAES]>; FeatureFuseAES,
FeatureLSLFast]>;
def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78",
"Cortex-A78 ARM processors", [ "Cortex-A78 ARM processors", [
FeatureCmpBccFusion, FeatureCmpBccFusion,
FeatureFuseAES, FeatureFuseAES,
FeatureLSLFast,
FeaturePostRAScheduler]>; FeaturePostRAScheduler]>;
def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily",
"CortexA78C", "CortexA78C",
"Cortex-A78C ARM processors", [ "Cortex-A78C ARM processors", [
FeatureCmpBccFusion, FeatureCmpBccFusion,
FeatureFuseAES, FeatureFuseAES,
FeatureLSLFast,
FeaturePostRAScheduler]>; FeaturePostRAScheduler]>;
def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710",
"Cortex-A710 ARM processors", [ "Cortex-A710 ARM processors", [
FeatureCmpBccFusion,
FeatureFuseAES, FeatureFuseAES,
FeaturePostRAScheduler, FeatureLSLFast,
FeatureCmpBccFusion]>; FeaturePostRAScheduler]>;
def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
"CortexR82", "CortexR82",
"Cortex-R82 ARM processors", [ "Cortex-R82 ARM processors", [
FeaturePostRAScheduler]>; FeaturePostRAScheduler]>;
def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", [ "Cortex-X1 ARM processors", [
FeatureCmpBccFusion, FeatureCmpBccFusion,
FeatureFuseAES, FeatureFuseAES,
FeatureLSLFast,
FeaturePostRAScheduler]>; FeaturePostRAScheduler]>;
def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
"Cortex-X2 ARM processors", [ "Cortex-X2 ARM processors", [
FeatureCmpBccFusion,
FeatureFuseAES, FeatureFuseAES,
FeaturePostRAScheduler, FeatureLSLFast,
FeatureCmpBccFusion]>; FeaturePostRAScheduler]>;
def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
"Fujitsu A64FX processors", [ "Fujitsu A64FX processors", [
FeaturePostRAScheduler, FeaturePostRAScheduler,
FeatureAggressiveFMA, FeatureAggressiveFMA,
FeatureArithmeticBccFusion, FeatureArithmeticBccFusion,
FeaturePredictableSelectIsExpensive FeaturePredictableSelectIsExpensive
]>; ]>;
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Linesdef TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
FeaturePredictableSelectIsExpensive, FeaturePredictableSelectIsExpensive,
FeatureZCZeroing, FeatureZCZeroing,
FeatureLSLFast, FeatureLSLFast,
FeatureSlowSTRQro FeatureSlowSTRQro
]>; ]>;
def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1",
"Neoverse E1 ARM processors", [ "Neoverse E1 ARM processors", [
FeaturePostRAScheduler, FeatureFuseAES,
FeatureFuseAES FeaturePostRAScheduler]>;
]>;
def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1",
"Neoverse N1 ARM processors", [ "Neoverse N1 ARM processors", [
FeaturePostRAScheduler,
FeatureFuseAES, FeatureFuseAES,
FeatureFuseAdrpAdd FeatureFuseAdrpAdd,
]>; FeatureLSLFast,
FeaturePostRAScheduler]>;
def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2",
"Neoverse N2 ARM processors", [ "Neoverse N2 ARM processors", [
FeaturePostRAScheduler, FeatureFuseAES,
FeatureFuseAES FeatureLSLFast,
]>; FeaturePostRAScheduler]>;
def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB",
"Neoverse 512-TVB ARM processors", [ "Neoverse 512-TVB ARM processors", [
FeaturePostRAScheduler, FeatureFuseAES,
FeatureFuseAES FeatureLSLFast,
]>; FeaturePostRAScheduler]>;
def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1",
"Neoverse V1 ARM processors", [ "Neoverse V1 ARM processors", [
FeatureFuseAES, FeatureFuseAES,
FeatureLSLFast,
FeaturePostRAScheduler]>; FeaturePostRAScheduler]>;
def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [ "Qualcomm Saphira processors", [
FeatureCustomCheapAsMoveHandling, FeatureCustomCheapAsMoveHandling,
FeaturePostRAScheduler, FeaturePostRAScheduler,
FeaturePredictableSelectIsExpensive, FeaturePredictableSelectIsExpensive,
FeatureZCZeroing, FeatureZCZeroing,
▲ Show 20 Lines • Show All 367 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+lsl-fast | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK0
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+lsl-fast | FileCheck %s --check-prefixes=CHECK,CHECK3
%struct.a = type [256 x i16] %struct.a = type [256 x i16]
%struct.b = type [256 x i32] %struct.b = type [256 x i32]
%struct.c = type [256 x i64] %struct.c = type [256 x i64]
declare void @foo() declare void @foo()
define i16 @halfword(%struct.a* %ctx, i32 %xor72) nounwind { define i16 @halfword(%struct.a* %ctx, i32 %xor72) nounwind {
; CHECK-LABEL: halfword: ; CHECK0-LABEL: halfword:
; CHECK: // %bb.0: ; CHECK0: // %bb.0:
; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill ; CHECK0-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK0-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: ubfx x21, x1, #9, #8 ; CHECK0-NEXT: ubfx x8, x1, #9, #8
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK0-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0 ; CHECK0-NEXT: lsl x21, x8, #1
; CHECK-NEXT: ldrh w20, [x0, x21, lsl #1] ; CHECK0-NEXT: mov x19, x0
; CHECK-NEXT: bl foo ; CHECK0-NEXT: ldrh w20, [x0, x21]
; CHECK-NEXT: mov w0, w20 ; CHECK0-NEXT: bl foo
; CHECK-NEXT: strh w20, [x19, x21, lsl #1] ; CHECK0-NEXT: mov w0, w20
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK0-NEXT: strh w20, [x19, x21]
; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload ; CHECK0-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK0-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK0-NEXT: ret
;
; CHECK3-LABEL: halfword:
; CHECK3: // %bb.0:
; CHECK3-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK3-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK3-NEXT: ubfx x21, x1, #9, #8
; CHECK3-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK3-NEXT: mov x19, x0
; CHECK3-NEXT: ldrh w20, [x0, x21, lsl #1]
; CHECK3-NEXT: bl foo
; CHECK3-NEXT: mov w0, w20
; CHECK3-NEXT: strh w20, [x19, x21, lsl #1]
; CHECK3-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK3-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK3-NEXT: ret
%shr81 = lshr i32 %xor72, 9 %shr81 = lshr i32 %xor72, 9
%conv82 = zext i32 %shr81 to i64 %conv82 = zext i32 %shr81 to i64
%idxprom83 = and i64 %conv82, 255 %idxprom83 = and i64 %conv82, 255
%arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83 %arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83
%result = load i16, i16* %arrayidx86, align 2 %result = load i16, i16* %arrayidx86, align 2
call void @foo() call void @foo()
store i16 %result, i16* %arrayidx86, align 2 store i16 %result, i16* %arrayidx86, align 2
ret i16 %result ret i16 %result
} }
define i32 @word(%struct.b* %ctx, i32 %xor72) nounwind { define i32 @word(%struct.b* %ctx, i32 %xor72) nounwind {
; CHECK-LABEL: word: ; CHECK0-LABEL: word:
; CHECK: // %bb.0: ; CHECK0: // %bb.0:
; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill ; CHECK0-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK0-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: ubfx x21, x1, #9, #8 ; CHECK0-NEXT: ubfx x8, x1, #9, #8
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK0-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0 ; CHECK0-NEXT: lsl x21, x8, #2
; CHECK-NEXT: ldr w20, [x0, x21, lsl #2] ; CHECK0-NEXT: mov x19, x0
; CHECK-NEXT: bl foo ; CHECK0-NEXT: ldr w20, [x0, x21]
; CHECK-NEXT: mov w0, w20 ; CHECK0-NEXT: bl foo
; CHECK-NEXT: str w20, [x19, x21, lsl #2] ; CHECK0-NEXT: mov w0, w20
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK0-NEXT: str w20, [x19, x21]
; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload ; CHECK0-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK0-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK0-NEXT: ret
;
; CHECK3-LABEL: word:
; CHECK3: // %bb.0:
; CHECK3-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK3-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK3-NEXT: ubfx x21, x1, #9, #8
; CHECK3-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK3-NEXT: mov x19, x0
; CHECK3-NEXT: ldr w20, [x0, x21, lsl #2]
; CHECK3-NEXT: bl foo
; CHECK3-NEXT: mov w0, w20
; CHECK3-NEXT: str w20, [x19, x21, lsl #2]
; CHECK3-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK3-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK3-NEXT: ret
%shr81 = lshr i32 %xor72, 9 %shr81 = lshr i32 %xor72, 9
%conv82 = zext i32 %shr81 to i64 %conv82 = zext i32 %shr81 to i64
%idxprom83 = and i64 %conv82, 255 %idxprom83 = and i64 %conv82, 255
%arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83 %arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83
%result = load i32, i32* %arrayidx86, align 4 %result = load i32, i32* %arrayidx86, align 4
call void @foo() call void @foo()
store i32 %result, i32* %arrayidx86, align 4 store i32 %result, i32* %arrayidx86, align 4
ret i32 %result ret i32 %result
} }
define i64 @doubleword(%struct.c* %ctx, i32 %xor72) nounwind { define i64 @doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
; CHECK-LABEL: doubleword: ; CHECK0-LABEL: doubleword:
; CHECK: // %bb.0: ; CHECK0: // %bb.0:
; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill ; CHECK0-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK0-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: ubfx x21, x1, #9, #8 ; CHECK0-NEXT: ubfx x8, x1, #9, #8
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK0-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0 ; CHECK0-NEXT: lsl x21, x8, #3
; CHECK-NEXT: ldr x20, [x0, x21, lsl #3] ; CHECK0-NEXT: mov x19, x0
; CHECK-NEXT: bl foo ; CHECK0-NEXT: ldr x20, [x0, x21]
; CHECK-NEXT: mov x0, x20 ; CHECK0-NEXT: bl foo
; CHECK-NEXT: str x20, [x19, x21, lsl #3] ; CHECK0-NEXT: mov x0, x20
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK0-NEXT: str x20, [x19, x21]
; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload ; CHECK0-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK0-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK0-NEXT: ret
;
; CHECK3-LABEL: doubleword:
; CHECK3: // %bb.0:
; CHECK3-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK3-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK3-NEXT: ubfx x21, x1, #9, #8
; CHECK3-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK3-NEXT: mov x19, x0
; CHECK3-NEXT: ldr x20, [x0, x21, lsl #3]
; CHECK3-NEXT: bl foo
; CHECK3-NEXT: mov x0, x20
; CHECK3-NEXT: str x20, [x19, x21, lsl #3]
; CHECK3-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK3-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK3-NEXT: ret
%shr81 = lshr i32 %xor72, 9 %shr81 = lshr i32 %xor72, 9
%conv82 = zext i32 %shr81 to i64 %conv82 = zext i32 %shr81 to i64
%idxprom83 = and i64 %conv82, 255 %idxprom83 = and i64 %conv82, 255
%arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83 %arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83
%result = load i64, i64* %arrayidx86, align 8 %result = load i64, i64* %arrayidx86, align 8
call void @foo() call void @foo()
store i64 %result, i64* %arrayidx86, align 8 store i64 %result, i64* %arrayidx86, align 8
ret i64 %result ret i64 %result
Show All 25 Lines
falsebb: falsebb:
%cmp2 = icmp sgt i64 %mul1, %mul2 %cmp2 = icmp sgt i64 %mul1, %mul2
br i1 %cmp2, label %exitbb, label %endbb br i1 %cmp2, label %exitbb, label %endbb
exitbb: exitbb:
ret i64 %mul1 ret i64 %mul1
endbb: endbb:
ret i64 %mul2 ret i64 %mul2
} }
define i64 @gep3(i64 *%p, i64 %b) {
; CHECK0-LABEL: gep3:
; CHECK0: // %bb.0:
; CHECK0-NEXT: lsl x9, x1, #3
; CHECK0-NEXT: mov x8, x0
; CHECK0-NEXT: ldr x0, [x0, x9]
; CHECK0-NEXT: str x1, [x8, x9]
; CHECK0-NEXT: ret
;
; CHECK3-LABEL: gep3:
; CHECK3: // %bb.0:
; CHECK3-NEXT: mov x8, x0
; CHECK3-NEXT: ldr x0, [x0, x1, lsl #3]
; CHECK3-NEXT: str x1, [x8, x1, lsl #3]
; CHECK3-NEXT: ret
%g = getelementptr inbounds i64, i64* %p, i64 %b
%l = load i64, i64* %g
store i64 %b, i64* %g
ret i64 %l
}
define i128 @gep4(i128 *%p, i128 %a, i64 %b) {
; CHECK-LABEL: gep4:
; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, x4, lsl #4
; CHECK-NEXT: ldp x0, x1, [x8]
; CHECK-NEXT: stp x2, x3, [x8]
; CHECK-NEXT: ret
%g = getelementptr inbounds i128, i128* %p, i64 %b
%l = load i128, i128* %g
store i128 %a, i128* %g
ret i128 %l
}
define i64 @addlsl3(i64 %a, i64 %b) {
; CHECK-LABEL: addlsl3:
; CHECK: // %bb.0:
; CHECK-NEXT: lsl x8, x0, #3
; CHECK-NEXT: add x9, x1, x8
; CHECK-NEXT: sub x8, x1, x8
; CHECK-NEXT: eor x0, x9, x8
; CHECK-NEXT: ret
%x = shl i64 %a, 3
%y = add i64 %b, %x
%z = sub i64 %b, %x
%r = xor i64 %y, %z
ret i64 %r
}
define i64 @addlsl4(i64 %a, i64 %b) {
; CHECK-LABEL: addlsl4:
; CHECK: // %bb.0:
; CHECK-NEXT: lsl x8, x0, #4
; CHECK-NEXT: add x9, x1, x8
; CHECK-NEXT: sub x8, x1, x8
; CHECK-NEXT: eor x0, x9, x8
; CHECK-NEXT: ret
%x = shl i64 %a, 4
%y = add i64 %b, %x
%z = sub i64 %b, %x
%r = xor i64 %y, %z
ret i64 %r
}