[InstCombine] Baseline tests for folding and-of-selects to xor

[marcauberer]

Summary

Baseline tests for: https://reviews.llvm.org/D133919

[marcauberer]

Rebase

[spatel]

Add negative tests where one of the select arms is a zero? Also, at least 1 test where the predicate is not equality, and a couple of tests where only one pair of the select operands are matching.

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

34

None of these commuted variants are logically different than the 1st test; they really just swap variable names. I don't think they're adding much value.

[marcauberer]

Add negative tests

[marcauberer]

Delete superflous commuted tests and reflect changes from eq to the ne test file

[marcauberer]

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

34

Removed the commuted variants.

[marcauberer]

Remove multi-use tests

[marcauberer]

Fix naming

[marcauberer]

Fix 0 select arm tests

[spatel]

This set of tests LGTM, but they are still not enough to provide coverage for the proposed code patch, so we need to add a few more tests. If the pattern-matching uses ValueTracking calls (isKnownNonZero and haveNoCommonBitsSet) then we should have some tests with non-constant select operands to exercise that. You can look at the implementations of those calls and reverse engineer tests that will match with variable operands.

[RKSimon]

@marcauberer reverse ping

[marcauberer]

Add test cases for checking non-immediate select arms

[marcauberer]

@spatel is one test case for icmpeq and one for icmpne enough for checking this?

[spatel]

In D134064#3880345, @marcauberer wrote:

@spatel is one test case for icmpeq and one for icmpne enough for checking this?

One for each of the non-constant cases should be enough. We're just trying to show that we can (and intended to) handle that kind of pattern via isKnownNonZero or whatever other ValueTracking calls that are used in the transform.

[marcauberer]

Add more tests for ValueTracking API calls

[marcauberer]

@spatel here we go! Everything should be tested now. Let me know if I am missing something.

[spatel]

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

152

This (and similar other tests) doesn't provide the coverage that you were hoping for.
This will be constant-folded before we ever reach the transform that we're hoping to unit-test.
That's why the test is already completely reduced to "false". :)

[marcauberer]

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

152

Okay, shall I remove them?

[spatel]

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

152

Yes - we don't want tests for other transforms as part of this patch.
But we still need tests to verify that the transform to be added is behaving as expected.
See if something like this works:
https://alive2.llvm.org/ce/z/2er3z7
...and adjust as needed (make the false arm of the selects non-immediate too), so the tests provide coverage for more of the pattern variations.

[marcauberer]

Test the right things:

[marcauberer]

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

152

The latest patchset should solve this ...

[spatel]

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

43

There are still a bunch of lines like this that reduce immediately to a constant. Those lines should be removed and replace the uses of that value with the constant in the rest of the test.

If the test doesn't provide any new coverage with that adjustment, then remove the whole test.

87

clear all but low bit?

166

This is a no-op. Was this supposed to be an 'or %z, 1'?

[marcauberer]

Apply improvements

[marcauberer]

Some of the negative tests still evaluate to 'false' or 'true'. I currently have no idea how to fix this ...

[spatel]

We need at least one positive test that exercises the known-bits logic. I was expecting the test that I posted (or something similar) to be in this mix.

Also, something's not working for the ne pred cases - those are miscompiles without a not at the end?

Let's reduce the complexity to make progress:

1. If a test is already reduced to true/false, remove it. It doesn't add coverage for the new code.
2. Defer the ne part to a follow-up patch. Just add a TODO comment about it in D133919 (also update the patch title so it's not so specific). We can leave the tests here or defer those too; whatever is easier to do is fine.

llvm/test/Transforms/InstCombine/select_and_icmpeq.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i1 @select_and_icmpeq_i32(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i32(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i32 2, i32 1
+  %s2 = select i1 %y, i32 2, i32 1
+  %and = and i32 %s1, %s2
+  %icmp = icmp eq i32 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i9(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i9(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[AND:%.*]] = and i9 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i9 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i9 3, i9 16
+  %s2 = select i1 %y, i9 3, i9 16
+  %and = and i9 %s2, %s1
+  %icmp = icmp eq i9 %and, 0
+  ret i1 %icmp
+}
+
+define <5 x i1> @select_and_icmpeq_i1vec(<5 x i1> %x, <5 x i1> %y) {
+; CHECK-LABEL: @select_and_icmpeq_i1vec(
+; CHECK-NEXT:    [[S1:%.*]] = select <5 x i1> [[X:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[S2:%.*]] = select <5 x i1> [[Y:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[AND:%.*]] = and <5 x i32> [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq <5 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT:    ret <5 x i1> [[ICMP]]
+;
+  %s1 = select <5 x i1> %x, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %s2 = select <5 x i1> %y, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %and = and <5 x i32> %s2, %s1
+  %icmp = icmp eq <5 x i32> %and, <i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <5 x i1> %icmp
+}
+
+define i1 @select_and_icmpeq_i8_negative_other_pred(i1 %x, i1 %y, i8 %u) {
+; CHECK-LABEL: @select_and_icmpeq_i8_negative_other_pred(
+; CHECK-NEXT:    ret i1 false
+;
+  %u0 = or i8 %u, 3   ; set two LSB
+  %v = and i8 %u0, 1  ; clear all bits, except LSB
+
+  %s1 = select i1 %x, i8 %v, i8 8
+  %s2 = select i1 %y, i8 %v, i8 8
+  %and = and i8 %s1, %s2
+  %icmp = icmp ult i8 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i16_negative_select_arm1_zero(i1 %x, i1 %y, i16 %z) {
+; CHECK-LABEL: @select_and_icmpeq_i16_negative_select_arm1_zero(
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[X:%.*]], i1 true, i1 [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %z0 = and i16 %z, -2 ; LSB must be clear
+  %t = or i16 %z0, 42  ; set some other bits
+
+  %s1 = select i1 %x, i16 0, i16 %t
+  %s2 = select i1 %y, i16 0, i16 %t
+  %and = and i16 %s1, %s2
+  %icmp = icmp eq i16 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i16_negative_select_arm2_zero(i1 %x, i1 %y, i16 %z) {
+; CHECK-LABEL: @select_and_icmpeq_i16_negative_select_arm2_zero(
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false
+; CHECK-NEXT:    [[NOT_:%.*]] = xor i1 [[TMP1]], true
+; CHECK-NEXT:    ret i1 [[NOT_]]
+;
+  %z0 = and i16 %z, -2 ; LSB must be clear
+  %t = or i16 %z0, 42  ; set some other bits
+
+  %s1 = select i1 %x, i16 %t, i16 0
+  %s2 = select i1 %y, i16 %t, i16 0
+  %and = and i16 %s1, %s2
+  %icmp = icmp eq i16 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i12_negative_one_select_pair_matching1(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i12_negative_one_select_pair_matching1(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 0, i12 4
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 2, i12 4
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i12 1, i12 4
+  %s2 = select i1 %y, i12 2, i12 4
+  %and = and i12 %s1, %s2
+  %icmp = icmp eq i12 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i13_negative_one_select_pair_matching2(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i13_negative_one_select_pair_matching2(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i13 2, i13 0
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i13 2, i13 4
+; CHECK-NEXT:    [[AND:%.*]] = and i13 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i13 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i13 2, i13 8
+  %s2 = select i1 %y, i13 2, i13 4
+  %and = and i13 %s1, %s2
+  %icmp = icmp eq i13 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_negative_non_imm_no_common_bits_set_i32(i1 %x, i1 %y, i32 %z, i32 %u) {
+; CHECK-LABEL: @select_and_icmpeq_negative_non_imm_no_common_bits_set_i32(
+; CHECK-NEXT:    ret i1 false
+;
+  %z0 = or i32 %z, 1   ; LSB is set
+  %t = or i32 %z0, 42  ; set some other bits
+
+  %u0 = or i32 %u, 3   ; set two LSB
+  %v = and i32 %u0, 1  ; only keep rightmost bit
+
+  %s1 = select i1 %x, i32 %t, i32 %v ; the LSB is set
+  %s2 = select i1 %y, i32 %t, i32 %v ; the LSB is set
+  %and = and i32 %s1, %s2
+  %icmp = icmp eq i32 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_negative_non_imm_is_known_non_zero_lhs_i12(i1 %x, i1 %y, i12 %z, i12 %u) {
+; CHECK-LABEL: @select_and_icmpeq_negative_non_imm_is_known_non_zero_lhs_i12(
+; CHECK-NEXT:    [[Z0:%.*]] = and i12 [[Z:%.*]], -2
+; CHECK-NEXT:    [[T:%.*]] = xor i12 [[Z0]], 42
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 [[T]], i12 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 [[T]], i12 1
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %z0 = and i12 %z, -2 ; LSB is clear
+  %t = xor i12 %z0, 42 ; set some other bits
+
+  %u0 = or i12 %u, 3   ; set two LSB
+  %v = and i12 %u0, 1  ; only keep rightmost bit
+
+  %s1 = select i1 %x, i12 %t, i12 %v
+  %s2 = select i1 %y, i12 %t, i12 %v
+  %and = and i12 %s2, %s1
+  %icmp = icmp eq i12 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_negative_non_imm_is_known_non_zero_rhs_i12(i1 %x, i1 %y, i12 %z, i12 %u) {
+; CHECK-LABEL: @select_and_icmpeq_negative_non_imm_is_known_non_zero_rhs_i12(
+; CHECK-NEXT:    [[Z0:%.*]] = and i12 [[Z:%.*]], -44
+; CHECK-NEXT:    [[T:%.*]] = or i12 [[Z0]], 42
+; CHECK-NEXT:    [[U0:%.*]] = and i12 [[U:%.*]], 1
+; CHECK-NEXT:    [[V:%.*]] = xor i12 [[U0]], 1
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 [[T]], i12 [[V]]
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 [[T]], i12 [[V]]
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %z0 = and i12 %z, -2 ; LSB is clear
+  %t = or i12 %z0, 42 ; set some other bits
+
+  %u0 = xor i12 %u, 3   ; set two LSB
+  %v = and i12 %u0, 1  ; clear all bits
+
+  %s1 = select i1 %x, i12 %t, i12 %v
+  %s2 = select i1 %y, i12 %t, i12 %v
+  %and = and i12 %s2, %s1
+  %icmp = icmp eq i12 %and, 0
+  ret i1 %icmp
+}

llvm/test/Transforms/InstCombine/select_and_icmpne.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i1 @select_and_icmpne_i32(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i32(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i32 2, i32 1
+  %s2 = select i1 %y, i32 2, i32 1
+  %and = and i32 %s1, %s2
+  %icmp = icmp ne i32 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i9(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i9(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[AND:%.*]] = and i9 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i9 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i9 3, i9 16
+  %s2 = select i1 %y, i9 3, i9 16
+  %and = and i9 %s2, %s1
+  %icmp = icmp ne i9 %and, 0
+  ret i1 %icmp
+}
+
+define <5 x i1> @select_and_icmpne_i1vec(<5 x i1> %x, <5 x i1> %y) {
+; CHECK-LABEL: @select_and_icmpne_i1vec(
+; CHECK-NEXT:    [[S1:%.*]] = select <5 x i1> [[X:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[S2:%.*]] = select <5 x i1> [[Y:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[AND:%.*]] = and <5 x i32> [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne <5 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT:    ret <5 x i1> [[ICMP]]
+;
+  %s1 = select <5 x i1> %x, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %s2 = select <5 x i1> %y, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %and = and <5 x i32> %s2, %s1
+  %icmp = icmp ne <5 x i32> %and, <i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <5 x i1> %icmp
+}
+
+define i1 @select_and_icmpne_i8_negative_other_pred(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i8_negative_other_pred(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i8 1, i8 8
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i8 1, i8 8
+; CHECK-NEXT:    [[AND:%.*]] = and i8 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i8 1, i8 8
+  %s2 = select i1 %y, i8 1, i8 8
+  %and = and i8 %s1, %s2
+  %icmp = icmp ugt i8 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i4_negative_select_arm1_zero(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i4_negative_select_arm1_zero(
+; CHECK-NEXT:    [[AND1_DEMORGAN:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND1:%.*]] = xor i1 [[AND1_DEMORGAN]], true
+; CHECK-NEXT:    ret i1 [[AND1]]
+;
+  %s1 = select i1 %x, i4 0, i4 1
+  %s2 = select i1 %y, i4 0, i4 1
+  %and = and i4 %s1, %s2
+  %icmp = icmp ne i4 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i4_negative_select_arm2_zero(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i4_negative_select_arm2_zero(
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %s1 = select i1 %x, i4 2, i4 0
+  %s2 = select i1 %y, i4 2, i4 0
+  %and = and i4 %s1, %s2
+  %icmp = icmp ne i4 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i12_negative_one_select_pair_matching1(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i12_negative_one_select_pair_matching1(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 0, i12 4
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 2, i12 4
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i12 1, i12 4
+  %s2 = select i1 %y, i12 2, i12 4
+  %and = and i12 %s1, %s2
+  %icmp = icmp ne i12 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i13_negative_one_select_pair_matching2(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i13_negative_one_select_pair_matching2(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i13 2, i13 0
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i13 2, i13 4
+; CHECK-NEXT:    [[AND:%.*]] = and i13 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i13 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i13 2, i13 8
+  %s2 = select i1 %y, i13 2, i13 4
+  %and = and i13 %s1, %s2
+  %icmp = icmp ne i13 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_negative_non_imm_no_common_bits_set_i32(i1 %x, i1 %y, i32 %z, i32 %u) {
+; CHECK-LABEL: @select_and_icmpne_negative_non_imm_no_common_bits_set_i32(
+; CHECK-NEXT:    ret i1 true
+;
+  %z0 = or i32 %z, 1   ; LSB is set
+  %t = or i32 %z0, 42  ; set some other bits
+
+  %u0 = or i32 %u, 3   ; set two LSB
+  %v = and i32 %u0, 1  ; only keep rightmost bit
+
+  %s1 = select i1 %x, i32 %t, i32 %v ; the LSB is set
+  %s2 = select i1 %y, i32 %t, i32 %v ; the LSB is set
+  %and = and i32 %s1, %s2
+  %icmp = icmp ne i32 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_negative_non_imm_is_known_non_zero_i12(i1 %x, i1 %y, i12 %z, i12 %u) {
+; CHECK-LABEL: @select_and_icmpne_negative_non_imm_is_known_non_zero_i12(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 [[Z:%.*]], i12 5
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 [[Z]], i12 5
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %z0 = and i12 %z, -2 ; LSB is clear
+  %t = or i12 %z0, 42 ; set some other bits
+
+  %u0 = xor i12 %u, 3   ; set two LSB
+  %v = and i12 %u0, 1  ; clear all bits
+
+  %s1 = select i1 %x, i12 %z, i12 5
+  %s2 = select i1 %y, i12 %z, i12 5
+  %and = and i12 %s2, %s1
+  %icmp = icmp ne i12 %and, 0
+  ret i1 %icmp
+}