Initial migration of AVR backend

[dylanmckay]

Summary

This patch adds the underlying infrastructure for an AVR backend to be included into LLVM. It is the first of a series of patches aimed at moving the out-of-tree AVR backend into the tree.

It consists of adding a new`Triple` target 'avr'.

[• tstellarAMD]

Hi,

I think this should be broken into 3 patches:

1. Triple + Calling Convention changes
2. ELF changes
3. Tablegen Changes.

Also you should teach llvm-readobj about the new ELF defines to make it easier for writing tests.

[dylanmckay]

Contain only triple-related changes

[arsenm]

This should include some tests in unittests/ADT/TripleTest.cpp

[dylanmckay]

Added tests to unittests/ADT/TripleTest.cpp.

[dylanmckay]

Removed the 'Atmel' vendor - it is unnecessary.

[dylanmckay]

Gentle ping.

[dylanmckay]

Ping.

[arsenm]

LGTM

[dylanmckay]

I don't have write access - can somebody merge this?

[dylanmckay]

Merged in r250492.

include/llvm/ADT/Triple.h

 public:
   enum ArchType {
     UnknownArch,
 
     arm,        // ARM (little endian): arm, armv.*, xscale
     armeb,      // ARM (big endian): armeb
     aarch64,    // AArch64 (little endian): aarch64
     aarch64_be, // AArch64 (big endian): aarch64_be
+    avr,        // AVR: Atmel AVR microcontroller
     bpfel,      // eBPF or extended BPF or 64-bit BPF (little endian)
     bpfeb,      // eBPF or extended BPF or 64-bit BPF (big endian)
     hexagon,    // Hexagon: hexagon
     mips,       // MIPS: mips, mipsallegrex
     mipsel,     // MIPSEL: mipsel, mipsallegrexel
     mips64,     // MIPS64: mips64
     mips64el,   // MIPS64EL: mips64el
     msp430,     // MSP430: msp430
enum SubArchType {
     KalimbaSubArch_v3,
     KalimbaSubArch_v4,
     KalimbaSubArch_v5
   };
   enum VendorType {
     UnknownVendor,
 
     Apple,
+    Atmel,
     PC,
     SCEI,
     BGP,
     BGQ,
     Freescale,
     IBM,
     ImaginationTechnologies,
     MipsTechnologies,

include/llvm/IR/CallingConv.h

enum {
 
     /// \brief Calling convention used by HipHop Virtual Machine (HHVM) to
     /// perform calls to and from translation cache, and for calling PHP
     /// functions.
     /// HHVM calling convention supports tail/sibling call elimination.
     HHVM = 81,
 
     /// \brief HHVM calling convention for invoking C/C++ helpers.
-    HHVM_C = 82
+    HHVM_C = 82,
+
+    /// Used for AVR interrupt routines.
+    AVR_INTR = 83,
+
+    /// AVR_SIGNAL - Used for AVR signal routines.
+    AVR_SIGNAL = 84,
+
+    /// Calling convention used for special multiplication RTLIB routines.
+    AVR_RT_MUL = 85,
+
+    /// Calling convention used for special division RTLIB routines.
+    AVR_RT_DIV = 86
   };
 } // End CallingConv namespace
 
 } // End llvm namespace
 
 #endif

include/llvm/Object/ELFObjectFile.h

StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
   case ELF::ELFCLASS32:
     switch (EF.getHeader()->e_machine) {
     case ELF::EM_386:
       return "ELF32-i386";
     case ELF::EM_X86_64:
       return "ELF32-x86-64";
     case ELF::EM_ARM:
       return (IsLittleEndian ? "ELF32-arm-little" : "ELF32-arm-big");
+    case ELF::EM_AVR:
+      return "ELF32-avr";
     case ELF::EM_HEXAGON:
       return "ELF32-hexagon";
     case ELF::EM_MIPS:
       return "ELF32-mips";
     case ELF::EM_PPC:
       return "ELF32-ppc";
     case ELF::EM_SPARC:
     case ELF::EM_SPARC32PLUS:
unsigned ELFObjectFile<ELFT>::getArch() const {
   case ELF::EM_386:
     return Triple::x86;
   case ELF::EM_X86_64:
     return Triple::x86_64;
   case ELF::EM_AARCH64:
     return Triple::aarch64;
   case ELF::EM_ARM:
     return Triple::arm;
+  case ELF::EM_AVR:
+    return Triple::avr;
   case ELF::EM_HEXAGON:
     return Triple::hexagon;
   case ELF::EM_MIPS:
     switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) {
     case ELF::ELFCLASS32:
       return IsLittleEndian ? Triple::mipsel : Triple::mips;
     case ELF::ELFCLASS64:
       return IsLittleEndian ? Triple::mips64el : Triple::mips64;

include/llvm/Support/ELF.h

enum : unsigned {
   EF_ARM_EABIMASK =       0xFF000000U
 };
 
 // ELF Relocation types for ARM
 enum {
 #include "ELFRelocs/ARM.def"
 };
 
+// AVR specific e_flags
+enum : unsigned {
+  EF_AVR_ARCH_AVR1    = 1,
+  EF_AVR_ARCH_AVR2    = 2,
+  EF_AVR_ARCH_AVR25   = 25,
+  EF_AVR_ARCH_AVR3    = 3,
+  EF_AVR_ARCH_AVR31   = 31,
+  EF_AVR_ARCH_AVR35   = 35,
+  EF_AVR_ARCH_AVR4    = 4,
+  EF_AVR_ARCH_AVR5    = 5,
+  EF_AVR_ARCH_AVR51   = 51,
+  EF_AVR_ARCH_AVR6    = 6,
+  EF_AVR_ARCH_AVRTINY = 100,
+  EF_AVR_ARCH_XMEGA1  = 101,
+  EF_AVR_ARCH_XMEGA2  = 102,
+  EF_AVR_ARCH_XMEGA3  = 103,
+  EF_AVR_ARCH_XMEGA4  = 104,
+  EF_AVR_ARCH_XMEGA5  = 105,
+  EF_AVR_ARCH_XMEGA6  = 106,
+  EF_AVR_ARCH_XMEGA7  = 107
+};
+
+// ELF Relocation types for AVR
+enum {
+#include "ELFRelocs/AVR.def"
+};
+
 // Mips Specific e_flags
 enum : unsigned {
   EF_MIPS_NOREORDER = 0x00000001, // Don't reorder instructions
   EF_MIPS_PIC       = 0x00000002, // Position independent code
   EF_MIPS_CPIC      = 0x00000004, // Call object with Position independent code
   EF_MIPS_ABI2      = 0x00000020, // File uses N32 ABI
   EF_MIPS_32BITMODE = 0x00000100, // Code compiled for a 64-bit machine
                                   // in 32-bit mode

include/llvm/Support/ELFRelocs/AVR.def

+
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_AVR_NONE,                  0)
+ELF_RELOC(R_AVR_32,                    1)
+ELF_RELOC(R_AVR_7_PCREL,               2)
+ELF_RELOC(R_AVR_13_PCREL,              3)
+ELF_RELOC(R_AVR_16,                    4)
+ELF_RELOC(R_AVR_16_PM,                 5)
+ELF_RELOC(R_AVR_LO8_LDI,               6)
+ELF_RELOC(R_AVR_HI8_LDI,               7)
+ELF_RELOC(R_AVR_HH8_LDI,               8)
+ELF_RELOC(R_AVR_LO8_LDI_NEG,           9)
+ELF_RELOC(R_AVR_HI8_LDI_NEG,          10)
+ELF_RELOC(R_AVR_HH8_LDI_NEG,          11)
+ELF_RELOC(R_AVR_LO8_LDI_PM,           12)
+ELF_RELOC(R_AVR_HI8_LDI_PM,           13)
+ELF_RELOC(R_AVR_HH8_LDI_PM,           14)
+ELF_RELOC(R_AVR_LO8_LDI_PM_NEG,       15)
+ELF_RELOC(R_AVR_HI8_LDI_PM_NEG,       16)
+ELF_RELOC(R_AVR_HH8_LDI_PM_NEG,       17)
+ELF_RELOC(R_AVR_CALL,                 18)
+ELF_RELOC(R_AVR_LDI,                  19)
+ELF_RELOC(R_AVR_6,                    20)
+ELF_RELOC(R_AVR_6_ADIW,               21)
+ELF_RELOC(R_AVR_MS8_LDI,              22)
+ELF_RELOC(R_AVR_MS8_LDI_NEG,          23)
+ELF_RELOC(R_AVR_LO8_LDI_GS,           24)
+ELF_RELOC(R_AVR_HI8_LDI_GS,           25)
+ELF_RELOC(R_AVR_8,                    26)
+ELF_RELOC(R_AVR_8_LO8,                27)
+ELF_RELOC(R_AVR_8_HI8,                28)
+ELF_RELOC(R_AVR_8_HLO8,               29)
+ELF_RELOC(R_AVR_SYM_DIFF,             30)
+ELF_RELOC(R_AVR_16_LDST,              31)
+ELF_RELOC(R_AVR_LDS_STS_16,           33)
+ELF_RELOC(R_AVR_PORT6,                34)
+ELF_RELOC(R_AVR_PORT5,                35)

include/llvm/Target/Target.td

class AsmParser {
   // function of the AsmParser class to call on every matched instruction.
   // This can be used to perform target specific instruction post-processing.
   string AsmParserInstCleanup  = "";
 
   // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
   // written register name matcher
   bit ShouldEmitMatchRegisterName = 1;
 
+  // ShouldEmitMatchRegisterAltName - Set to false if the target needs a hand
+  // written register alternative name matcher
+  bit ShouldEmitMatchRegisterAltName = 0;
+
   /// Does the instruction mnemonic allow '.'
   bit MnemonicContainsDot = 0;
 }
 def DefaultAsmParser : AsmParser;
 
 //===----------------------------------------------------------------------===//
 // AsmParserVariant - Subtargets can have multiple different assembly parsers
 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be

lib/Support/Triple.cpp

 const char *Triple::getArchTypeName(ArchType Kind) {
   switch (Kind) {
   case UnknownArch: return "unknown";
 
   case aarch64:     return "aarch64";
   case aarch64_be:  return "aarch64_be";
   case arm:         return "arm";
   case armeb:       return "armeb";
+  case avr:         return "avr";
   case bpfel:       return "bpfel";
   case bpfeb:       return "bpfeb";
   case hexagon:     return "hexagon";
   case mips:        return "mips";
   case mipsel:      return "mipsel";
   case mips64:      return "mips64";
   case mips64el:    return "mips64el";
   case msp430:      return "msp430";
const char *Triple::getArchTypePrefix(ArchType Kind) {
   case aarch64:
   case aarch64_be:  return "aarch64";
 
   case arm:
   case armeb:
   case thumb:
   case thumbeb:     return "arm";
 
+  case avr:         return "avr";
+
   case ppc64:
   case ppc64le:
   case ppc:         return "ppc";
 
   case mips:
   case mipsel:
   case mips64:
   case mips64el:    return "mips";
const char *Triple::getArchTypePrefix(ArchType Kind) {
   }
 }
 
 const char *Triple::getVendorTypeName(VendorType Kind) {
   switch (Kind) {
   case UnknownVendor: return "unknown";
 
   case Apple: return "apple";
+  case Atmel: return "atmel";
   case PC: return "pc";
   case SCEI: return "scei";
   case BGP: return "bgp";
   case BGQ: return "bgq";
   case Freescale: return "fsl";
   case IBM: return "ibm";
   case ImaginationTechnologies: return "img";
   case MipsTechnologies: return "mti";

 Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
   Triple::ArchType BPFArch(parseBPFArch(Name));
   return StringSwitch<Triple::ArchType>(Name)
     .Case("aarch64", aarch64)
     .Case("aarch64_be", aarch64_be)
     .Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
     .Case("arm", arm)
     .Case("armeb", armeb)
+    .Case("avr", avr)
     .StartsWith("bpf", BPFArch)
     .Case("mips", mips)
     .Case("mipsel", mipsel)
     .Case("mips64", mips64)
     .Case("mips64el", mips64el)
     .Case("msp430", msp430)
     .Case("ppc64", ppc64)
     .Case("ppc32", ppc)
auto AT = StringSwitch<Triple::ArchType>(ArchName)
     .Case("xscaleeb", Triple::armeb)
     .Case("aarch64", Triple::aarch64)
     .Case("aarch64_be", Triple::aarch64_be)
     .Case("arm64", Triple::aarch64)
     .Case("arm", Triple::arm)
     .Case("armeb", Triple::armeb)
     .Case("thumb", Triple::thumb)
     .Case("thumbeb", Triple::thumbeb)
+    .Case("avr", Triple::avr)
     .Case("msp430", Triple::msp430)
     .Cases("mips", "mipseb", "mipsallegrex", Triple::mips)
     .Cases("mipsel", "mipsallegrexel", Triple::mipsel)
     .Cases("mips64", "mips64eb", Triple::mips64)
     .Case("mips64el", Triple::mips64el)
     .Case("r600", Triple::r600)
     .Case("amdgcn", Triple::amdgcn)
     .Case("hexagon", Triple::hexagon)
static Triple::ArchType parseArch(StringRef ArchName) {
   }
 
   return AT;
 }
 
 static Triple::VendorType parseVendor(StringRef VendorName) {
   return StringSwitch<Triple::VendorType>(VendorName)
     .Case("apple", Triple::Apple)
+    .Case("atmel", Triple::Atmel)
     .Case("pc", Triple::PC)
     .Case("scei", Triple::SCEI)
     .Case("bgp", Triple::BGP)
     .Case("bgq", Triple::BGQ)
     .Case("fsl", Triple::Freescale)
     .Case("ibm", Triple::IBM)
     .Case("img", Triple::ImaginationTechnologies)
     .Case("mti", Triple::MipsTechnologies)
void Triple::setOSAndEnvironmentName(StringRef Str) {
   setTriple(getArchName() + "-" + getVendorName() + "-" + Str);
 }
 
 static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   switch (Arch) {
   case llvm::Triple::UnknownArch:
     return 0;
 
+  case llvm::Triple::avr:
   case llvm::Triple::msp430:
     return 16;
 
   case llvm::Triple::arm:
   case llvm::Triple::armeb:
   case llvm::Triple::hexagon:
   case llvm::Triple::le32:
   case llvm::Triple::mips:

 
 Triple Triple::get32BitArchVariant() const {
   Triple T(*this);
   switch (getArch()) {
   case Triple::UnknownArch:
   case Triple::aarch64:
   case Triple::aarch64_be:
   case Triple::amdgcn:
+  case Triple::avr:
   case Triple::bpfel:
   case Triple::bpfeb:
   case Triple::msp430:
   case Triple::systemz:
   case Triple::ppc64le:
     T.setArch(UnknownArch);
     break;
 

 }
 
 Triple Triple::get64BitArchVariant() const {
   Triple T(*this);
   switch (getArch()) {
   case Triple::UnknownArch:
   case Triple::arm:
   case Triple::armeb:
+  case Triple::avr:
   case Triple::hexagon:
   case Triple::kalimba:
   case Triple::msp430:
   case Triple::r600:
   case Triple::tce:
   case Triple::thumb:
   case Triple::thumbeb:
   case Triple::xcore:

 
 Triple Triple::getBigEndianArchVariant() const {
   Triple T(*this);
   switch (getArch()) {
   case Triple::UnknownArch:
   case Triple::amdgcn:
   case Triple::amdil64:
   case Triple::amdil:
+  case Triple::avr:
   case Triple::hexagon:
   case Triple::hsail64:
   case Triple::hsail:
   case Triple::kalimba:
   case Triple::le32:
   case Triple::le64:
   case Triple::msp430:
   case Triple::nvptx64:
case Triple::thumbeb:
     T.setArch(UnknownArch);
     break;
 
   case Triple::aarch64:
   case Triple::amdgcn:
   case Triple::amdil64:
   case Triple::amdil:
   case Triple::arm:
+  case Triple::avr:
   case Triple::bpfel:
   case Triple::hexagon:
   case Triple::hsail64:
   case Triple::hsail:
   case Triple::kalimba:
   case Triple::le32:
   case Triple::le64:
   case Triple::mips64el:

utils/TableGen/AsmMatcherEmitter.cpp

static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
   OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
 
   StringMatcher("Name", Matches, OS).Emit();
 
   OS << "  return 0;\n";
   OS << "}\n\n";
 }
 
+/// Emit the function to match a string to the target
+/// specific register enum.
+static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
+                                     raw_ostream &OS) {
+  // Construct the match list.
+  std::vector<StringMatcher::StringPair> Matches;
+  const auto &Regs = Target.getRegBank().getRegisters();
+  for (const CodeGenRegister &Reg : Regs) {
+
+    auto AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
+
+    for(auto AltName : AltNames) {
+      AltName = StringRef(AltName).trim();
+
+      // don't handle empty alternative names
+      if(AltName.empty())
+        continue;
+
+      Matches.emplace_back(AltName,
+                           "return " + utostr(Reg.EnumValue) + ";");
+    }
+  }
+
+  OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
+
+  StringMatcher("Name", Matches, OS).Emit();
+
+  OS << "  return 0;\n";
+  OS << "}\n\n";
+}
+
 static const char *getMinimalTypeForRange(uint64_t Range) {
   assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
   if (Range > 0xFFFFFFFFULL)
     return "uint64_t";
   if (Range > 0xFFFF)
     return "uint32_t";
   if (Range > 0xFF)
     return "uint16_t";
void AsmMatcherEmitter::run(raw_ostream &OS) {
   // Emit the subtarget feature enumeration.
   emitSubtargetFeatureFlagEnumeration(Info, OS);
 
   // Emit the function to match a register name to number.
   // This should be omitted for Mips target
   if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
     emitMatchRegisterName(Target, AsmParser, OS);
 
+  if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName")) {
+    emitMatchRegisterAltName(Target, AsmParser, OS);
+  }
+
   OS << "#endif // GET_REGISTER_MATCHER\n\n";
 
   OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
   OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
 
   // Generate the helper function to get the names for subtarget features.
   emitGetSubtargetFeatureName(Info, OS);