[LoongArch] Support register-register-addressed FPR load and store

[xen0n]

Seems good, thanks!

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

 def : PatFPSelectcc<SETULT, FCMP_CULT_S, FSEL_S, FPR32>;
 def : PatFPSelectcc<SETULE, FCMP_CULE_S, FSEL_S, FPR32>;
 def : PatFPSelectcc<SETUNE, FCMP_CUNE_S, FSEL_S, FPR32>;
 def : PatFPSelectcc<SETUO,  FCMP_CUN_S,  FSEL_S, FPR32>;
 
 /// Loads
 
 defm : LdPat<load, FLD_S, f32>;
+def : RegRegLdPat<load, FLDX_S, f32>;
 
 /// Stores
 
 defm : StPat<store, FST_S, FPR32, f32>;
+def : RegRegStPat<store, FSTX_S, FPR32, f32>;
 
 /// Floating point constants
 
 def : Pat<(f32 fpimm0), (MOVGR2FR_W R0)>;
 def : Pat<(f32 fpimm0neg), (FNEG_S (MOVGR2FR_W R0))>;
 def : Pat<(f32 fpimm1), (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1)))>;
 
 // FP Conversion

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

 def : PatFPSelectcc<SETULT, FCMP_CULT_D, FSEL_D, FPR64>;
 def : PatFPSelectcc<SETULE, FCMP_CULE_D, FSEL_D, FPR64>;
 def : PatFPSelectcc<SETUNE, FCMP_CUNE_D, FSEL_D, FPR64>;
 def : PatFPSelectcc<SETUO,  FCMP_CUN_D,  FSEL_D, FPR64>;
 
 /// Loads
 
 defm : LdPat<load, FLD_D, f64>;
+def : RegRegLdPat<load, FLDX_D, f64>;
 
 /// Stores
 
 defm : StPat<store, FST_D, FPR64, f64>;
+def : RegRegStPat<store, FSTX_D, FPR64, f64>;
 
 /// FP conversion operations
 
 def : Pat<(loongarch_ftint FPR64:$src), (FTINTRZ_W_D FPR64:$src)>;
 def : Pat<(f64 (loongarch_ftint FPR64:$src)), (FTINTRZ_L_D FPR64:$src)>;
 def : Pat<(loongarch_ftint FPR32:$src), (FTINTRZ_L_S FPR32:$src)>;
 
 // f64 -> f32

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 defm : LdPat<sextloadi32, LD_W, i64>;
 defm : LdPat<extloadi32, LD_W, i64>;
 defm : LdPat<zextloadi32, LD_WU, i64>;
 defm : LdPat<load, LD_D, i64>;
 } // Predicates = [IsLA64]
 
 // LA64 register-register-addressed loads
 let Predicates = [IsLA64] in {
-class RegRegLdPat<PatFrag LoadOp, LAInst Inst>
-  : Pat<(i64 (LoadOp (add BaseAddr:$rj, GPR:$rk))),
+class RegRegLdPat<PatFrag LoadOp, LAInst Inst, ValueType vt>
+  : Pat<(vt (LoadOp (add BaseAddr:$rj, GPR:$rk))),
         (Inst BaseAddr:$rj, GPR:$rk)>;
 
-def : RegRegLdPat<extloadi8, LDX_B>;
-def : RegRegLdPat<sextloadi8, LDX_B>;
-def : RegRegLdPat<zextloadi8, LDX_BU>;
-def : RegRegLdPat<extloadi16, LDX_H>;
-def : RegRegLdPat<sextloadi16, LDX_H>;
-def : RegRegLdPat<zextloadi16, LDX_HU>;
-def : RegRegLdPat<extloadi32, LDX_W>;
-def : RegRegLdPat<sextloadi32, LDX_W>;
-def : RegRegLdPat<zextloadi32, LDX_WU>;
-def : RegRegLdPat<load, LDX_D>;
+def : RegRegLdPat<extloadi8, LDX_B, i64>;
+def : RegRegLdPat<sextloadi8, LDX_B, i64>;
+def : RegRegLdPat<zextloadi8, LDX_BU, i64>;
+def : RegRegLdPat<extloadi16, LDX_H, i64>;
+def : RegRegLdPat<sextloadi16, LDX_H, i64>;
+def : RegRegLdPat<zextloadi16, LDX_HU, i64>;
+def : RegRegLdPat<extloadi32, LDX_W, i64>;
+def : RegRegLdPat<sextloadi32, LDX_W, i64>;
+def : RegRegLdPat<zextloadi32, LDX_WU, i64>;
+def : RegRegLdPat<load, LDX_D, i64>;
 } // Predicates = [IsLA64]
 
 /// Stores
 
 multiclass StPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy,
                  ValueType vt> {
   def : Pat<(StoreOp (vt StTy:$rd), BaseAddr:$rj),
             (Inst StTy:$rd, BaseAddr:$rj, 0)>;
def : Pat<(truncstorei32 (i64 GPR:$rd),
                          (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
           (STPTR_W GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
 def : Pat<(store (i64 GPR:$rd), (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
           (STPTR_D GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
 } // Predicates = [IsLA64]
 
 // LA64 register-register-addressed stores
 let Predicates = [IsLA64] in {
-class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy>
-  : Pat<(StoreOp (i64 StTy:$rd), (add BaseAddr:$rj, GPR:$rk)),
+class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy,
+                  ValueType vt>
+  : Pat<(StoreOp (vt StTy:$rd), (add BaseAddr:$rj, GPR:$rk)),
         (Inst StTy:$rd, BaseAddr:$rj, GPR:$rk)>;
 
-def : RegRegStPat<truncstorei8, STX_B, GPR>;
-def : RegRegStPat<truncstorei16, STX_H, GPR>;
-def : RegRegStPat<truncstorei32, STX_W, GPR>;
-def : RegRegStPat<store, STX_D, GPR>;
+def : RegRegStPat<truncstorei8, STX_B, GPR, i64>;
+def : RegRegStPat<truncstorei16, STX_H, GPR, i64>;
+def : RegRegStPat<truncstorei32, STX_W, GPR, i64>;
+def : RegRegStPat<store, STX_D, GPR, i64>;
 } // Predicates = [IsLA64]
 
 /// Atomic loads and stores
 
 def : Pat<(atomic_fence timm, timm), (DBAR 0)>;
 
 defm : LdPat<atomic_load_8, LD_B>;
 defm : LdPat<atomic_load_16, LD_H>;

llvm/test/CodeGen/LoongArch/ir-instruction/load-store-fp.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32F
+; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32D
+; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64F
+; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64D
+
+define float @fldx_s(ptr %a, i64 %idx) nounwind {
+; LA32F-LABEL: fldx_s:
+; LA32F:       # %bb.0:
+; LA32F-NEXT:    slli.w $a1, $a1, 2
+; LA32F-NEXT:    fldx.s $fa0, $a0, $a1
+; LA32F-NEXT:    ret
+;
+; LA32D-LABEL: fldx_s:
+; LA32D:       # %bb.0:
+; LA32D-NEXT:    slli.w $a1, $a1, 2
+; LA32D-NEXT:    fldx.s $fa0, $a0, $a1
+; LA32D-NEXT:    ret
+;
+; LA64F-LABEL: fldx_s:
+; LA64F:       # %bb.0:
+; LA64F-NEXT:    slli.d $a1, $a1, 2
+; LA64F-NEXT:    fldx.s $fa0, $a0, $a1
+; LA64F-NEXT:    ret
+;
+; LA64D-LABEL: fldx_s:
+; LA64D:       # %bb.0:
+; LA64D-NEXT:    slli.d $a1, $a1, 2
+; LA64D-NEXT:    fldx.s $fa0, $a0, $a1
+; LA64D-NEXT:    ret
+  %1 = getelementptr float, ptr %a, i64 %idx
+  %2 = load float, ptr %1
+  ret float %2
+}
+
+define double @fldx_d(ptr %a, i64 %idx) nounwind {
+; LA32F-LABEL: fldx_d:
+; LA32F:       # %bb.0:
+; LA32F-NEXT:    slli.w $a1, $a1, 3
+; LA32F-NEXT:    add.w $a1, $a0, $a1
+; LA32F-NEXT:    ld.w $a0, $a1, 0
+; LA32F-NEXT:    ld.w $a1, $a1, 4
+; LA32F-NEXT:    ret
+;
+; LA32D-LABEL: fldx_d:
+; LA32D:       # %bb.0:
+; LA32D-NEXT:    slli.w $a1, $a1, 3
+; LA32D-NEXT:    fldx.d $fa0, $a0, $a1
+; LA32D-NEXT:    ret
+;
+; LA64F-LABEL: fldx_d:
+; LA64F:       # %bb.0:
+; LA64F-NEXT:    slli.d $a1, $a1, 3
+; LA64F-NEXT:    ldx.d $a0, $a0, $a1
+; LA64F-NEXT:    ret
+;
+; LA64D-LABEL: fldx_d:
+; LA64D:       # %bb.0:
+; LA64D-NEXT:    slli.d $a1, $a1, 3
+; LA64D-NEXT:    fldx.d $fa0, $a0, $a1
+; LA64D-NEXT:    ret
+  %1 = getelementptr double, ptr %a, i64 %idx
+  %2 = load double, ptr %1
+  ret double %2
+}
+
+define void @fstx_s(ptr %dst, i64 %idx, float %val) nounwind {
+; LA32F-LABEL: fstx_s:
+; LA32F:       # %bb.0:
+; LA32F-NEXT:    slli.w $a1, $a1, 2
+; LA32F-NEXT:    fstx.s $fa0, $a0, $a1
+; LA32F-NEXT:    ret
+;
+; LA32D-LABEL: fstx_s:
+; LA32D:       # %bb.0:
+; LA32D-NEXT:    slli.w $a1, $a1, 2
+; LA32D-NEXT:    fstx.s $fa0, $a0, $a1
+; LA32D-NEXT:    ret
+;
+; LA64F-LABEL: fstx_s:
+; LA64F:       # %bb.0:
+; LA64F-NEXT:    slli.d $a1, $a1, 2
+; LA64F-NEXT:    fstx.s $fa0, $a0, $a1
+; LA64F-NEXT:    ret
+;
+; LA64D-LABEL: fstx_s:
+; LA64D:       # %bb.0:
+; LA64D-NEXT:    slli.d $a1, $a1, 2
+; LA64D-NEXT:    fstx.s $fa0, $a0, $a1
+; LA64D-NEXT:    ret
+  %1 = getelementptr float, ptr %dst, i64 %idx
+  store float %val, ptr %1
+  ret void
+}
+
+define void @fstx_d(ptr %dst, i64 %idx, double %val) nounwind {
+; LA32F-LABEL: fstx_d:
+; LA32F:       # %bb.0:
+; LA32F-NEXT:    slli.w $a1, $a1, 3
+; LA32F-NEXT:    add.w $a0, $a0, $a1
+; LA32F-NEXT:    st.w $a4, $a0, 4
+; LA32F-NEXT:    st.w $a3, $a0, 0
+; LA32F-NEXT:    ret
+;
+; LA32D-LABEL: fstx_d:
+; LA32D:       # %bb.0:
+; LA32D-NEXT:    slli.w $a1, $a1, 3
+; LA32D-NEXT:    fstx.d $fa0, $a0, $a1
+; LA32D-NEXT:    ret
+;
+; LA64F-LABEL: fstx_d:
+; LA64F:       # %bb.0:
+; LA64F-NEXT:    slli.d $a1, $a1, 3
+; LA64F-NEXT:    stx.d $a2, $a0, $a1
+; LA64F-NEXT:    ret
+;
+; LA64D-LABEL: fstx_d:
+; LA64D:       # %bb.0:
+; LA64D-NEXT:    slli.d $a1, $a1, 3
+; LA64D-NEXT:    fstx.d $fa0, $a0, $a1
+; LA64D-NEXT:    ret
+  %1 = getelementptr double, ptr %dst, i64 %idx
+  store double %val, ptr %1
+  ret void
+}