[LoongArch] Supports brcond with 21 bit offsets

[xen0n]

LGTM except the nit.

llvm/test/CodeGen/LoongArch/bnez-beqz.ll

8

Isn't the "testcase name" misleading? It certainly is meant to exercise the bnez pattern with i32 icmp, so it could be better to name it bnez_i32 instead.

Same with other cases.

[gonglingqin]

llvm/test/CodeGen/LoongArch/bnez-beqz.ll

8

Thanks, I will change that.

[gonglingqin]

Address @xen0n's comments.

[SixWeining]

LGTM.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 def : BccSwapPat<setle, BGE>;
 def : BccSwapPat<setugt, BLTU>;
 def : BccSwapPat<setule, BGEU>;
 
 // An extra pattern is needed for a brcond without a setcc (i.e. where the
 // condition was calculated elsewhere).
 def : Pat<(brcond GPR:$rj, bb:$imm21), (BNEZ GPR:$rj, bb:$imm21)>;
 
+def : Pat<(brcond (GRLenVT (seteq GPR:$rj, 0)), bb:$imm21),
+          (BEQZ GPR:$rj, bb:$imm21)>;
+def : Pat<(brcond (GRLenVT (setne GPR:$rj, 0)), bb:$imm21),
+          (BNEZ GPR:$rj, bb:$imm21)>;
+
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
 def PseudoBR : Pseudo<(outs), (ins simm26_lsl2:$imm26), [(br bb:$imm26)]>,
                PseudoInstExpansion<(B simm26_lsl2:$imm26)>;
 
 let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
 def PseudoBRIND : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16), []>,
                   PseudoInstExpansion<(JIRL R0, GPR:$rj, simm16_lsl2:$imm16)>;
 

llvm/test/CodeGen/LoongArch/bnez-beqz.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+declare void @bar()
+
+define void @bnez_i32(i32 signext %0) nounwind {
+; LA32-LABEL: bnez_i32:
+; LA32:       # %bb.0: # %start
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    bnez $a0, .LBB0_2
+; LA32-NEXT:  # %bb.1: # %t
+; LA32-NEXT:    bl bar
+; LA32-NEXT:  .LBB0_2: # %f
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: bnez_i32:
+; LA64:       # %bb.0: # %start
+; LA64-NEXT:    addi.d $sp, $sp, -16
+; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:    bnez $a0, .LBB0_2
+; LA64-NEXT:  # %bb.1: # %t
+; LA64-NEXT:    bl bar
+; LA64-NEXT:  .LBB0_2: # %f
+; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 16
+; LA64-NEXT:    ret
+start:
+  %1 = icmp eq i32 %0, 0
+  br i1 %1, label %t, label %f
+
+t:
+  tail call void @bar()
+  br label %f
+
+f:
+  ret void
+}
+
+define void @beqz_i32(i32 signext %0) nounwind {
+; LA32-LABEL: beqz_i32:
+; LA32:       # %bb.0: # %start
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    beqz $a0, .LBB1_2
+; LA32-NEXT:  # %bb.1: # %t
+; LA32-NEXT:    bl bar
+; LA32-NEXT:  .LBB1_2: # %f
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: beqz_i32:
+; LA64:       # %bb.0: # %start
+; LA64-NEXT:    addi.d $sp, $sp, -16
+; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:    beqz $a0, .LBB1_2
+; LA64-NEXT:  # %bb.1: # %t
+; LA64-NEXT:    bl bar
+; LA64-NEXT:  .LBB1_2: # %f
+; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 16
+; LA64-NEXT:    ret
+start:
+  %1 = icmp ne i32 %0, 0
+  br i1 %1, label %t, label %f
+
+t:
+  tail call void @bar()
+  br label %f
+
+f:
+  ret void
+}
+
+define void @bnez_i64(i64 %0) nounwind {
+; LA32-LABEL: bnez_i64:
+; LA32:       # %bb.0: # %start
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    or $a0, $a0, $a1
+; LA32-NEXT:    bnez $a0, .LBB2_2
+; LA32-NEXT:  # %bb.1: # %t
+; LA32-NEXT:    bl bar
+; LA32-NEXT:  .LBB2_2: # %f
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: bnez_i64:
+; LA64:       # %bb.0: # %start
+; LA64-NEXT:    addi.d $sp, $sp, -16
+; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:    bnez $a0, .LBB2_2
+; LA64-NEXT:  # %bb.1: # %t
+; LA64-NEXT:    bl bar
+; LA64-NEXT:  .LBB2_2: # %f
+; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 16
+; LA64-NEXT:    ret
+start:
+  %1 = icmp eq i64 %0, 0
+  br i1 %1, label %t, label %f
+
+t:
+  tail call void @bar()
+  br label %f
+
+f:
+  ret void
+}
+
+define void @beqz_i64(i64 %0) nounwind {
+; LA32-LABEL: beqz_i64:
+; LA32:       # %bb.0: # %start
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    or $a0, $a0, $a1
+; LA32-NEXT:    beqz $a0, .LBB3_2
+; LA32-NEXT:  # %bb.1: # %t
+; LA32-NEXT:    bl bar
+; LA32-NEXT:  .LBB3_2: # %f
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: beqz_i64:
+; LA64:       # %bb.0: # %start
+; LA64-NEXT:    addi.d $sp, $sp, -16
+; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:    beqz $a0, .LBB3_2
+; LA64-NEXT:  # %bb.1: # %t
+; LA64-NEXT:    bl bar
+; LA64-NEXT:  .LBB3_2: # %f
+; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 16
+; LA64-NEXT:    ret
+start:
+  %1 = icmp ne i64 %0, 0
+  br i1 %1, label %t, label %f
+
+t:
+  tail call void @bar()
+  br label %f
+
+f:
+  ret void
+}