[LoongArch] Add codegen support for bswap

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

72

As Table 1 described, revb.2h is available on LA32.
So for i16, we can use it.

llvm/test/CodeGen/LoongArch/bswap.ll

3

The standard way is to use two dashes.

llc --help | grep mtriple
  --mtriple=<string>                                                    - Override target triple for module

And --verify-machineinstrs:

llc --help-hidden | grep verify-machineinstrs
  --verify-machineinstrs                                                - Verify generated machine code

And --check-prefix:

FileCheck --help | grep check-prefix
  --check-prefix=<string>        - Prefix to use from check file (defaults to 'CHECK')

34–40

How about:

revb.2h $a0, $a0
rotri.w $a0, 16

[xen0n]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

72

I looked at the original document《龙芯架构 32 位精简版参考手册》 which doesn't contain this instruction, maybe it's because it's actually describing the LA32 Primary ISA? But apparently it described way more instructions than the tiny subset suitable for university courses.

I'll change anyway. Thanks for the fact checking.

llvm/test/CodeGen/LoongArch/bswap.ll

34–40

As revb.2h can be used in this case, I'll change this. Thanks.

[xen0n]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

72

Although it's really weird that REVB.W isn't being listed, even though it doesn't involve any operation wider than 32 bits... Maybe there are hardware implementation concerns but I'm not a HW designer so my intuition can fail me. Anyway rotri.w works.

[xen0n]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

72

Although it's really weird that REVB.W isn't being listed

My bad; there isn't REVB.W but only REVB.2W. LoongArch is not orthogonal... (many swear words omitted)

[xen0n]

Enable revb.2h on LA32, use revb.2h + rotri.w to implement bswap.i32 on LA32.

[xen0n]

fix typo

[xen0n]

forgot to fix the FileCheck header

[SixWeining]

Other parts LGTM.

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

159

Another approach:

let Predicates = [IsLA32] in {
def : Pat<(bswap GPR:$rj), (ROTRI_W (REVB_2H GPR:$rj), 16)>;
}

I'm not sure which approach is better. But this one uses less code.

[xen0n]

Simplify code by making more use of tblgen

[xen0n]

I submitted too early after realizing tblgen could be used for bswap.i32 on LA32, fixed anyway. Thanks for the suggestion.

[xen0n]

apparently setOperationAction for Legal ops can be omitted

[SixWeining]

LGTM. Thanks!

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

enum NodeType : unsigned {
   MOVGR2FR_W_LA64,
   MOVFR2GR_S_LA64,
 
   FTINT,
 
   BSTRINS,
   BSTRPICK,
 
+  // Byte swapping operations
+  REVB_2H,
+  REVB_2W,
 };
 } // end namespace LoongArchISD
 
 class LoongArchTargetLowering : public TargetLowering {
   const LoongArchSubtarget &Subtarget;
 
 public:
   explicit LoongArchTargetLowering(const TargetMachine &TM,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

if (Subtarget.is64Bit()) {
     setOperationAction(ISD::SRA, MVT::i32, Custom);
     setOperationAction(ISD::SRL, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::BITCAST, MVT::i32, Custom);
     if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
       setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
   }
 
+  // LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and
+  // the narrower REVB.W does not exist. But LA32 does have REVB.2H, so i16
+  // and i32 could still be byte-swapped relatively cheaply.
+  setOperationAction(ISD::BSWAP, MVT::i16, Custom);
+  if (Subtarget.is64Bit()) {
+    setOperationAction(ISD::BSWAP, MVT::i32, Custom);
+  }
+
   static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
                                                ISD::SETUGT, ISD::SETUGE};
 
   if (Subtarget.hasBasicF()) {
     setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
   }
   if (Subtarget.hasBasicD()) {
case ISD::SRL_PARTS:
     return lowerShiftRightParts(Op, DAG, false);
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
     // This can be called for an i32 shift amount that needs to be promoted.
     assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     return SDValue();
+  case ISD::BSWAP:
+    return SDValue();
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
   case ISD::FP_TO_SINT:
     return lowerFP_TO_SINT(Op, DAG);
   case ISD::BITCAST:
     return lowerBITCAST(Op, DAG);
   case ISD::FP_TO_UINT:
     return SDValue();
   case ISD::UINT_TO_FP:
     return lowerUINT_TO_FP(Op, DAG);
   case ISD::VASTART:
     return lowerVASTART(Op, DAG);
   }
 }
 
 SDValue LoongArchTargetLowering::lowerVASTART(SDValue Op,
                                               SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   auto *FuncInfo = MF.getInfo<LoongArchMachineFunctionInfo>();
 
   SDLoc DL(Op);
   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
                                  getPointerTy(MF.getDataLayout()));
 
case ISD::FP_TO_UINT: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     auto &TLI = DAG.getTargetLoweringInfo();
     SDValue Tmp1, Tmp2;
     TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG);
     Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1));
     break;
   }
+  case ISD::BSWAP: {
+    SDValue Src = N->getOperand(0);
+    EVT VT = N->getValueType(0);
+    assert((VT == MVT::i16 || VT == MVT::i32) &&
+           "Unexpected custom legalization");
+    MVT GRLenVT = Subtarget.getGRLenVT();
+    SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src);
+    SDValue Tmp;
+    switch (VT.getSizeInBits()) {
+    default:
+      llvm_unreachable("Unexpected operand width");
+    case 16:
+      Tmp = DAG.getNode(LoongArchISD::REVB_2H, DL, GRLenVT, NewSrc);
+      break;
+    case 32:
+      // Only LA64 will get to here due to the size mismatch between VT and
+      // GRLenVT, LA32 lowering is directly defined in LoongArchInstrInfo.
+      Tmp = DAG.getNode(LoongArchISD::REVB_2W, DL, GRLenVT, NewSrc);
+      break;
+    }
+    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Tmp));
+    break;
+  }
   }
 }
 
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  const LoongArchSubtarget &Subtarget) {
   if (DCI.isBeforeLegalizeOps())
     return SDValue();
case LoongArchISD::node:                                                     \
     NODE_NAME_CASE(SLL_W)
     NODE_NAME_CASE(SRA_W)
     NODE_NAME_CASE(SRL_W)
     NODE_NAME_CASE(BSTRINS)
     NODE_NAME_CASE(BSTRPICK)
     NODE_NAME_CASE(MOVGR2FR_W_LA64)
     NODE_NAME_CASE(MOVFR2GR_S_LA64)
     NODE_NAME_CASE(FTINT)
+    NODE_NAME_CASE(REVB_2H)
+    NODE_NAME_CASE(REVB_2W)
   }
 #undef NODE_NAME_CASE
   return nullptr;
 }
 
 //===----------------------------------------------------------------------===//
 //                     Calling Convention Implementation
 //===----------------------------------------------------------------------===//

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

def loongarch_ret : SDNode<"LoongArchISD::RET", SDTNone,
                            [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def loongarch_sll_w : SDNode<"LoongArchISD::SLL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_sra_w : SDNode<"LoongArchISD::SRA_W", SDT_LoongArchIntBinOpW>;
 def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_bstrins
     : SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
 def loongarch_bstrpick
     : SDNode<"LoongArchISD::BSTRPICK", SDT_LoongArchBStrPick>;
+def loongarch_revb_2h : SDNode<"LoongArchISD::REVB_2H", SDTUnaryOp>;
+def loongarch_revb_2w : SDNode<"LoongArchISD::REVB_2W", SDTUnaryOp>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
 class ImmAsmOperand<string prefix, int width, string suffix>
     : AsmOperandClass {
   let Name = prefix # "Imm" # width # suffix;

 
 let Predicates = [IsLA64] in {
 def : Pat<(loongarch_bstrins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
           (BSTRINS_D GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd)>;
 def : Pat<(loongarch_bstrpick GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
           (BSTRPICK_D GPR:$rj, uimm6:$msbd, uimm6:$lsbd)>;
 } // Predicates = [IsLA64]
 
+/// Byte-swapping
+
+def : Pat<(loongarch_revb_2h GPR:$rj), (REVB_2H GPR:$rj)>;
+
+let Predicates = [IsLA32] in {
+def : Pat<(bswap GPR:$rj), (ROTRI_W (REVB_2H GPR:$rj), 16)>;
+} // Predicates = [IsLA32]
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_revb_2w GPR:$rj), (REVB_2W GPR:$rj)>;
+def : Pat<(bswap GPR:$rj), (REVB_D GPR:$rj)>;
+} // Predicates = [IsLA64]
+
 /// Loads
 
 multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
   def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
   def : Pat<(vt (LoadOp (AddLike BaseAddr:$rj, simm12:$imm12))),
             (Inst BaseAddr:$rj, simm12:$imm12)>;
 }
 

llvm/test/CodeGen/LoongArch/bswap.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=loongarch32 --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc -mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+
+declare i16 @llvm.bswap.i16(i16)
+declare i32 @llvm.bswap.i32(i32)
+declare i48 @llvm.bswap.i48(i48)
+declare i64 @llvm.bswap.i64(i64)
+declare i80 @llvm.bswap.i80(i80)
+declare i128 @llvm.bswap.i128(i128)
+
+define i16 @test_bswap_i16(i16 %a) nounwind {
+; LA32-LABEL: test_bswap_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    revb.2h $a0, $a0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: test_bswap_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    revb.2h $a0, $a0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %tmp = call i16 @llvm.bswap.i16(i16 %a)
+  ret i16 %tmp
+}
+
+define i32 @test_bswap_i32(i32 %a) nounwind {
+; LA32-LABEL: test_bswap_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    revb.2h $a0, $a0
+; LA32-NEXT:    rotri.w $a0, $a0, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: test_bswap_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    revb.2w $a0, $a0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %tmp = call i32 @llvm.bswap.i32(i32 %a)
+  ret i32 %tmp
+}
+
+define i64 @test_bswap_i64(i64 %a) nounwind {
+; LA32-LABEL: test_bswap_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    revb.2h $a1, $a1
+; LA32-NEXT:    rotri.w $a2, $a1, 16
+; LA32-NEXT:    revb.2h $a0, $a0
+; LA32-NEXT:    rotri.w $a1, $a0, 16
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: test_bswap_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    revb.d $a0, $a0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %tmp = call i64 @llvm.bswap.i64(i64 %a)
+  ret i64 %tmp
+}
+
+;; Bswap on non-native integer widths.
+
+define i48 @test_bswap_i48(i48 %a) nounwind {
+; LA32-LABEL: test_bswap_i48:
+; LA32:       # %bb.0:
+; LA32-NEXT:    revb.2h $a1, $a1
+; LA32-NEXT:    rotri.w $a1, $a1, 16
+; LA32-NEXT:    srli.w $a1, $a1, 16
+; LA32-NEXT:    revb.2h $a0, $a0
+; LA32-NEXT:    rotri.w $a2, $a0, 16
+; LA32-NEXT:    slli.w $a0, $a2, 16
+; LA32-NEXT:    or $a0, $a1, $a0
+; LA32-NEXT:    srli.w $a1, $a2, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: test_bswap_i48:
+; LA64:       # %bb.0:
+; LA64-NEXT:    revb.d $a0, $a0
+; LA64-NEXT:    srli.d $a0, $a0, 16
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %tmp = call i48 @llvm.bswap.i48(i48 %a)
+  ret i48 %tmp
+}
+
+define i80 @test_bswap_i80(i80 %a) nounwind {
+; LA32-LABEL: test_bswap_i80:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ld.w $a2, $a1, 0
+; LA32-NEXT:    revb.2h $a2, $a2
+; LA32-NEXT:    rotri.w $a2, $a2, 16
+; LA32-NEXT:    ld.w $a3, $a1, 4
+; LA32-NEXT:    revb.2h $a3, $a3
+; LA32-NEXT:    rotri.w $a3, $a3, 16
+; LA32-NEXT:    srli.w $a4, $a3, 16
+; LA32-NEXT:    slli.w $a5, $a2, 16
+; LA32-NEXT:    or $a4, $a5, $a4
+; LA32-NEXT:    srli.w $a2, $a2, 16
+; LA32-NEXT:    st.h $a2, $a0, 8
+; LA32-NEXT:    st.w $a4, $a0, 4
+; LA32-NEXT:    slli.w $a2, $a3, 16
+; LA32-NEXT:    ld.w $a1, $a1, 8
+; LA32-NEXT:    revb.2h $a1, $a1
+; LA32-NEXT:    rotri.w $a1, $a1, 16
+; LA32-NEXT:    srli.w $a1, $a1, 16
+; LA32-NEXT:    or $a1, $a1, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: test_bswap_i80:
+; LA64:       # %bb.0:
+; LA64-NEXT:    revb.d $a1, $a1
+; LA64-NEXT:    srli.d $a1, $a1, 48
+; LA64-NEXT:    revb.d $a2, $a0
+; LA64-NEXT:    slli.d $a0, $a2, 16
+; LA64-NEXT:    or $a0, $a1, $a0
+; LA64-NEXT:    srli.d $a1, $a2, 48
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %tmp = call i80 @llvm.bswap.i80(i80 %a)
+  ret i80 %tmp
+}
+
+define i128 @test_bswap_i128(i128 %a) nounwind {
+; LA32-LABEL: test_bswap_i128:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ld.w $a2, $a1, 0
+; LA32-NEXT:    revb.2h $a2, $a2
+; LA32-NEXT:    rotri.w $a2, $a2, 16
+; LA32-NEXT:    st.w $a2, $a0, 12
+; LA32-NEXT:    ld.w $a2, $a1, 4
+; LA32-NEXT:    revb.2h $a2, $a2
+; LA32-NEXT:    rotri.w $a2, $a2, 16
+; LA32-NEXT:    st.w $a2, $a0, 8
+; LA32-NEXT:    ld.w $a2, $a1, 8
+; LA32-NEXT:    revb.2h $a2, $a2
+; LA32-NEXT:    rotri.w $a2, $a2, 16
+; LA32-NEXT:    st.w $a2, $a0, 4
+; LA32-NEXT:    ld.w $a1, $a1, 12
+; LA32-NEXT:    revb.2h $a1, $a1
+; LA32-NEXT:    rotri.w $a1, $a1, 16
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: test_bswap_i128:
+; LA64:       # %bb.0:
+; LA64-NEXT:    revb.d $a2, $a1
+; LA64-NEXT:    revb.d $a1, $a0
+; LA64-NEXT:    move $a0, $a2
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %tmp = call i128 @llvm.bswap.i128(i128 %a)
+  ret i128 %tmp
+}