[mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions

[zbuljan]

Summary

The patch implements microMIPSDSP instructions: ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB.

[dsanders]

lib/Target/Mips/MicroMipsDSPInstrFormats.td

13–14

It's very important that you put these in the correct category. PredicateControl only works if each sub-list is a mutually exclusive group.

HasDSP is an InsnPredicate. InMicroMips is an AdditionalPredicate.

20

Please rename 'instr_asm' to 'opstr' to match MMCDSPInst. instr_asm is likely to be confused for assembly mnemonics which is not how it's used (the assembly syntax is defined by the *_DESC class).

32–33

Likewise

lib/Target/Mips/MipsDSPInstrFormats.td

31–33

HasDSPR2 is an InsnPredicate not an EncodingPredicate.

test/MC/Disassembler/Mips/micromips_dsp.txt

1

(about filename):
I've been trying to organize test/MC/Disassembler/Mips the same way as test/MC/Mips but other work has been taking priority so I haven't renamed all the files yet.

Could you name this file test/MC/Disassembler/Mips/micromips-dsp/valid.txt?

5

Nit: The blank lines in this file are unnecessary. If any double-spaced files have crept back in could you fix them? Thanks

test/MC/Disassembler/Mips/micromips_dspr2.txt

1

(about filename):
I've been trying to organize test/MC/Disassembler/Mips the same way as test/MC/Mips but other work has been taking priority so I haven't renamed all the files yet.

Could you name this file test/MC/Disassembler/Mips/micromips-dspr2/valid.txt?

2

Likewise

test/MC/Mips/micromips32r6/micromips-dsp-instructions.s

1

(about filename):
I didn't spot this on the previous patch, but this is in the wrong directory too. At test/MC/Mips we have a directory for each ISA and each ASE. DSP is an ASE so this should be in test/MC/Mips/micromips-dsp/valid.txt

I'll correct the repo.

[zbuljan]

InMicroMips set as AdditionalPredicates.
'instr_asm' parameter renamed to 'opstr'.
HasDSPR2 set as InsnPredicates.
Assembler and disassembler test files renamed and moved to micromips-dsp and micromips-dspr2 subfolders.
Deleted unnecessary blank lines.

[dsanders]

LGTM. I've mentioned a merge conflict you'll get due to upstream changes below.

test/MC/Mips/micromips32r6/micromips-dsp-instructions.s

1

You'll need to apply this to test/MC/Mips/micromips-dsp/valid.txt instead of test/MC/Mips/micromips32r6/micromips-dsp-instructions.s since I've fixed the layout in the repo.

lib/Target/Mips/MicroMipsDSPInstrFormats.td

 //===-- MicroMipsDSPInstrFormats.td - Micromips DSP Instruction Formats -*-
 //tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 class MMDSPInst<string opstr = "">
     : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
   let EncodingPredicates = [HasDSP];
+  let InsnPredicates = [InMicroMips];
   string BaseOpcode = opstr;
   string Arch = "mmdsp";
   let DecoderNamespace = "MicroMips";
 }
 
-class POOL32A_3R_FMT<bits<11> op> : MMDSPInst {
+class POOL32A_3R_FMT<string instr_asm, bits<11> op> : MMDSPInst<instr_asm> {
   bits<5> rd;
   bits<5> rs;
   bits<5> rt;
 
   let Inst{31-26} = 0b000000;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-11} = rd;
   let Inst{10-0}  = op;
 }
+
+class POOL32A_3RB0_FMT<string instr_asm, bits<10> op>
+    : MMDSPInst<instr_asm> {
+  bits<5> rd;
+  bits<5> rs;
+  bits<5> rt;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10}    = 0b0;
+  let Inst{9-0}   = op;
+}

lib/Target/Mips/MicroMipsDSPInstrInfo.td

 //===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes MicroMips DSP instructions.
 //
 //===----------------------------------------------------------------------===//
 
 // Instruction encoding.
-class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>;
+class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>;
+class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>;
+class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>;
+class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>;
+class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>;
+class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>;
+class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>;
+class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>;
+class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>;
+class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
+class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>;
+class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>;
+class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>;
+class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>;
+class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>;
 
 // Instruction defs.
-// MIPS DSP Rev 1
-def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS;
+// microMIPS DSP Rev 1
+def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
+def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
+def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC;
+def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
+def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC;
+def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC;
+def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC;
+// microMIPS DSP Rev 2
+def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
+def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
+def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
+def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
+def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
+def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
+def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2;
+def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;

lib/Target/Mips/MipsDSPInstrFormats.td

 
 def HasDSP : Predicate<"Subtarget->hasDSP()">,
              AssemblerPredicate<"FeatureDSP">;
 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
                AssemblerPredicate<"FeatureDSPR2">;
 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
                AssemblerPredicate<"FeatureDSPR3">;
 
+class ISA_DSPR2 {
+  list<Predicate> EncodingPredicates = [HasDSPR2];
+}
+
 // Fields.
 class Field6<bits<6> val> {
   bits<6> V = val;
 }
 
 def SPECIAL3_OPCODE : Field6<0b011111>;
 def REGIMM_OPCODE : Field6<0b000001>;
 

lib/Target/Mips/MipsDSPInstrInfo.td

 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                         InstrItinClass itin, RegisterOperand ROD,
                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
   dag OutOperandList = (outs ROD:$rd);
   dag InOperandList = (ins ROS:$rs, ROT:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
   InstrItinClass Itinerary = itin;
+  string BaseOpcode = instr_asm;
 }
 
 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                            InstrItinClass itin, RegisterOperand ROD,
                            RegisterOperand ROS = ROD> {
   dag OutOperandList = (outs ROD:$rd);
   dag InOperandList = (ins ROS:$rs);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");

 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                          InstrItinClass itin, RegisterOperand ROD,
                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
   dag OutOperandList = (outs ROD:$rd);
   dag InOperandList = (ins ROS:$rs, ROT:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
   InstrItinClass Itinerary = itin;
+  string BaseOpcode = instr_asm;
 }
 
 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                        SDPatternOperator ImmOp, InstrItinClass itin> {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
   list<dag> Pattern =  [(set GPR32Opnd:$rt,

 
 // Pseudos.
 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
                                                 NoItinerary>, Uses<[DSPPos]>;
 
 // Instruction defs.
 // MIPS DSP Rev 1
 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
-def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
+def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
-def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
-def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
+def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
+def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
-def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
+def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
-def ADDSC : ADDSC_ENC, ADDSC_DESC;
-def ADDWC : ADDWC_ENC, ADDWC_DESC;
+def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
+def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
 def MODSUB : MODSUB_ENC, MODSUB_DESC;
 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;

 def SHILOV : SHILOV_ENC, SHILOV_DESC;
 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
 def RDDSP : RDDSP_ENC, RDDSP_DESC;
 def WRDSP : WRDSP_ENC, WRDSP_DESC;
 
 // MIPS DSP Rev 2
 let Predicates = [HasDSPR2] in {
 
-def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
-def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
+def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
+def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
-def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
-def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
+def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
+def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
-def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
-def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
+def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
+def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
-def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
-def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
+def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
+def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;

test/MC/Disassembler/Mips/micromips_dsp.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips  -mattr=+dsp | FileCheck %s
 
 0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
 
+0x00 0xa4 0x1c 0xcd # CHECK: addu_s.qb $3, $4, $5
+
+0x00 0xa4 0x1b 0x85 # CHECK: addsc $3, $4, $5
+
+0x00 0xa4 0x1b 0xc5 # CHECK: addwc $3, $4, $5
+
+0x00 0xa4 0x18 0x0d # CHECK: addq.ph $3, $4, $5
+
+0x00 0xa4 0x1c 0x0d # CHECK: addq_s.ph $3, $4, $5
+
+0x00 0xa4 0x1b 0x05 # CHECK: addq_s.w $3, $4, $5

test/MC/Disassembler/Mips/micromips_dspr2.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips  -mattr=+dspr2 | FileCheck %s
+
+0x00 0xa4 0x18 0x4d # CHECK: addqh.ph $3, $4, $5
+
+0x00 0xa4 0x1c 0x4d # CHECK: addqh_r.ph $3, $4, $5
+
+0x00 0xa4 0x18 0x8d # CHECK: addqh.w $3, $4, $5
+
+0x00 0xa4 0x1c 0x8d # CHECK: addqh_r.w $3, $4, $5
+
+0x00 0xa4 0x19 0x0d # CHECK: addu.ph $3, $4, $5
+
+0x00 0xa4 0x1d 0x0d # CHECK: addu_s.ph $3, $4, $5
+
+0x00 0xa4 0x19 0x4d # CHECK: adduh.qb $3, $4, $5
+
+0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5

test/MC/Mips/micromips32r6/micromips-dsp-instructions.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
 
   .set noat
   addu.qb $3, $4, $5           # CHECK: addu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xcd]
+  addu_s.qb $3, $4, $5         # CHECK: addu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1c,0xcd]
+  addsc $3, $4, $5             # CHECK: addsc $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0x85]
+  addwc $3, $4, $5             # CHECK: addwc $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0xc5]
+  addq.ph $3, $4, $5           # CHECK: addq.ph $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x0d]
+  addq_s.ph $3, $4, $5         # CHECK: addq_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1c,0x0d]
+  addq_s.w $3, $4, $5          # CHECK: addq_s.w $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x05]
 

test/MC/Mips/micromips32r6/micromips-dspr2-instructions.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
+
+  .set noat
+  addqh.ph $3, $4, $5          # CHECK: addqh.ph $3, $4, $5     # encoding: [0x00,0xa4,0x18,0x4d]
+  addqh_r.ph $3, $4, $5        # CHECK: addqh_r.ph $3, $4, $5   # encoding: [0x00,0xa4,0x1c,0x4d]
+  addqh.w $3, $4, $5           # CHECK: addqh.w $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x8d]
+  addqh_r.w $3, $4, $5         # CHECK: addqh_r.w $3, $4, $5    # encoding: [0x00,0xa4,0x1c,0x8d]
+  addu.ph $3, $4, $5           # CHECK: addu.ph $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x0d]
+  addu_s.ph $3, $4, $5         # CHECK: addu_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1d,0x0d]
+  adduh.qb $3, $4, $5          # CHECK: adduh.qb $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x4d]
+  adduh_r.qb $3, $4, $5        # CHECK: adduh_r.qb $3, $4, $5   # encoding: [0x00,0xa4,0x1d,0x4d]