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Zlatko BuljanZlatko Buljan
Zlatko Buljan
authored and
Zlatko Buljan
committedOct 19, 2015
[mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
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7 files changed

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-21
lines changed

7 files changed

+90
-21
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‎llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,3 +64,16 @@ class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
6464
let Inst{13-6} = op;
6565
let Inst{5-0} = 0b111100;
6666
}
67+
68+
class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
69+
bits<5> rd;
70+
bits<5> rs;
71+
bits<5> rt;
72+
73+
let Inst{31-26} = 0b000000;
74+
let Inst{25-21} = rt;
75+
let Inst{20-16} = rs;
76+
let Inst{15-11} = rd;
77+
let Inst{10} = 0b0;
78+
let Inst{9-0} = op;
79+
}

‎llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td

Lines changed: 34 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,21 @@
1212
//===----------------------------------------------------------------------===//
1313

1414
// Instruction encoding.
15+
class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>;
16+
class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>;
17+
class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>;
18+
class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>;
19+
class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>;
20+
class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>;
21+
class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>;
22+
class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>;
23+
class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>;
1524
class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
25+
class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>;
26+
class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>;
27+
class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>;
28+
class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>;
29+
class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>;
1630
class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>;
1731
class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>;
1832
class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>;
@@ -50,18 +64,17 @@ class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
5064
"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
5165

5266
// microMIPS DSP Rev 1
67+
def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
68+
def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
69+
def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC;
5370
def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
71+
def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC;
72+
def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC;
73+
def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC;
5474
def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC;
5575
def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC;
5676
def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC;
5777
def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC;
58-
// microMIPS DSP Rev 2
59-
def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
60-
def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
61-
ISA_DSPR2;
62-
def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
63-
ISA_DSPR2;
64-
def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
6578
def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC;
6679
def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC;
6780
def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC;
@@ -74,3 +87,17 @@ def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC;
7487
// microMIPS DSP Rev 2
7588
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
7689
ISA_DSPR2;
90+
def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
91+
def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
92+
def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
93+
def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
94+
def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
95+
def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
96+
def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2;
97+
def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
98+
def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
99+
def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
100+
ISA_DSPR2;
101+
def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
102+
ISA_DSPR2;
103+
def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;

‎llvm/lib/Target/Mips/MipsDSPInstrInfo.td

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -365,6 +365,7 @@ class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
365365
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
366366
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
367367
InstrItinClass Itinerary = itin;
368+
string BaseOpcode = instr_asm;
368369
}
369370

370371
class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -1079,17 +1080,17 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
10791080
// Instruction defs.
10801081
// MIPS DSP Rev 1
10811082
def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1082-
def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1083+
def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
10831084
def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
10841085
def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1085-
def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1086-
def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1086+
def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1087+
def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
10871088
def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
10881089
def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1089-
def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1090+
def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
10901091
def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1091-
def ADDSC : ADDSC_ENC, ADDSC_DESC;
1092-
def ADDWC : ADDWC_ENC, ADDWC_DESC;
1092+
def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1093+
def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
10931094
def MODSUB : MODSUB_ENC, MODSUB_DESC;
10941095
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
10951096
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
@@ -1195,24 +1196,24 @@ def WRDSP : WRDSP_ENC, WRDSP_DESC;
11951196
// MIPS DSP Rev 2
11961197
let Predicates = [HasDSPR2] in {
11971198

1198-
def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1199-
def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1199+
def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1200+
def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
12001201
def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
12011202
def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
12021203
def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
12031204
def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
12041205
def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
12051206
def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1206-
def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1207-
def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1207+
def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1208+
def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
12081209
def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
12091210
def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1210-
def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1211-
def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1211+
def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1212+
def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
12121213
def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
12131214
def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1214-
def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1215-
def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1215+
def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1216+
def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
12161217
def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
12171218
def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
12181219
def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;

‎llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,12 @@
11
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
22

33
0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
4+
0x00 0xa4 0x1c 0xcd # CHECK: addu_s.qb $3, $4, $5
5+
0x00 0xa4 0x1b 0x85 # CHECK: addsc $3, $4, $5
6+
0x00 0xa4 0x1b 0xc5 # CHECK: addwc $3, $4, $5
7+
0x00 0xa4 0x18 0x0d # CHECK: addq.ph $3, $4, $5
8+
0x00 0xa4 0x1c 0x0d # CHECK: addq_s.ph $3, $4, $5
9+
0x00 0xa4 0x1b 0x05 # CHECK: addq_s.w $3, $4, $5
410
0x00 0x65 0x42 0xbc # CHECK: dpaq_s.w.ph $ac1, $5, $3
511
0x00 0x64 0x92 0xbc # CHECK: dpaq_sa.l.w $ac2, $4, $3
612
0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4

‎llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,13 @@
11
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
22

3+
0x00 0xa4 0x18 0x4d # CHECK: addqh.ph $3, $4, $5
4+
0x00 0xa4 0x1c 0x4d # CHECK: addqh_r.ph $3, $4, $5
5+
0x00 0xa4 0x18 0x8d # CHECK: addqh.w $3, $4, $5
6+
0x00 0xa4 0x1c 0x8d # CHECK: addqh_r.w $3, $4, $5
7+
0x00 0xa4 0x19 0x0d # CHECK: addu.ph $3, $4, $5
8+
0x00 0xa4 0x1d 0x0d # CHECK: addu_s.ph $3, $4, $5
9+
0x00 0xa4 0x19 0x4d # CHECK: adduh.qb $3, $4, $5
10+
0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5
311
0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4
412
0x00 0x43 0x00 0xbc # CHECK: dpa.w.ph $ac0, $3, $2
513
0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7

‎llvm/test/MC/Mips/micromips-dsp/valid.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,12 @@
22

33
.set noat
44
addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]
5+
addu_s.qb $3, $4, $5 # CHECK: addu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0xcd]
6+
addsc $3, $4, $5 # CHECK: addsc $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x85]
7+
addwc $3, $4, $5 # CHECK: addwc $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0xc5]
8+
addq.ph $3, $4, $5 # CHECK: addq.ph $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x0d]
9+
addq_s.ph $3, $4, $5 # CHECK: addq_s.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0x0d]
10+
addq_s.w $3, $4, $5 # CHECK: addq_s.w $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x05]
511
dpaq_s.w.ph $ac1, $5, $3 # CHECK: dpaq_s.w.ph $ac1, $5, $3 # encoding: [0x00,0x65,0x42,0xbc]
612
dpaq_sa.l.w $ac2, $4, $3 # CHECK: dpaq_sa.l.w $ac2, $4, $3 # encoding: [0x00,0x64,0x92,0xbc]
713
dpau.h.qbl $ac1, $3, $4 # CHECK: dpau.h.qbl $ac1, $3, $4 # encoding: [0x00,0x83,0x60,0xbc]

‎llvm/test/MC/Mips/micromips-dspr2/valid.s

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,14 @@
11
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
22

33
.set noat
4+
addqh.ph $3, $4, $5 # CHECK: addqh.ph $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x4d]
5+
addqh_r.ph $3, $4, $5 # CHECK: addqh_r.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0x4d]
6+
addqh.w $3, $4, $5 # CHECK: addqh.w $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x8d]
7+
addqh_r.w $3, $4, $5 # CHECK: addqh_r.w $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0x8d]
8+
addu.ph $3, $4, $5 # CHECK: addu.ph $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x0d]
9+
addu_s.ph $3, $4, $5 # CHECK: addu_s.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x0d]
10+
adduh.qb $3, $4, $5 # CHECK: adduh.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x4d]
11+
adduh_r.qb $3, $4, $5 # CHECK: adduh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x4d]
412
absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x00,0x64,0x01,0x3c]
513
dpa.w.ph $ac0, $3, $2 # CHECK: dpa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x00,0xbc]
614
dpaqx_s.w.ph $ac3, $12, $7 # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc]

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