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Differential D131265

Fixed sm version for .and bmma operator.
ClosedPublic

Authored by JackAKirk on Aug 5 2022, 8:30 AM.

Details

Reviewers
tra
Commits
rG3e0e5568a6a8: [CUDA] Fixed sm version constrain for __bmma_m8n8k128_mma_and_popc_b1.
Summary

As stated here (https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-wmma-mma):

".and operation in single-bit wmma requires sm_80 or higher."

Diff Detail

Event Timeline

JackAKirk created this revision.Aug 5 2022, 8:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2022, 8:30 AM
Herald added subscribers: mattd, gchakrabarti, asavonic. · View Herald Transcript
JackAKirk requested review of this revision.Aug 5 2022, 8:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2022, 8:30 AM
Herald added subscribers: cfe-commits, jholewinski. · View Herald Transcript
Harbormaster completed remote builds in B179525: Diff 450302.Aug 5 2022, 9:10 AM
tra accepted this revision.Aug 5 2022, 9:50 AM

Good catch. LGTM.

This revision is now accepted and ready to land.Aug 5 2022, 9:50 AM
JackAKirk added a comment.Aug 5 2022, 11:03 AM
In D131265#3702594, @tra wrote:

Good catch. LGTM.

Thanks. If you could land it for me that would be much appreciated. I don't have the rights.

This revision was landed with ongoing or failed builds.Aug 5 2022, 12:14 PM
Closed by commit rG3e0e5568a6a8: [CUDA] Fixed sm version constrain for __bmma_m8n8k128_mma_and_popc_b1. (authored by JackAKirk, committed by tra). · Explain Why
This revision was automatically updated to reflect the committed changes.
tra added a commit: rG3e0e5568a6a8: [CUDA] Fixed sm version constrain for __bmma_m8n8k128_mma_and_popc_b1..
tra added a comment.Aug 5 2022, 12:14 PM

Looks like the tests needed to be updated (and I've found one bug which explains how we've missed this).

JackAKirk added a comment.Aug 8 2022, 9:01 AM
In D131265#3702954, @tra wrote:

Looks like the tests needed to be updated (and I've found one bug which explains how we've missed this).

Ah yes I see it. Thanks for updating the tests.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
2 lines

Diff 450302

clang/include/clang/Basic/BuiltinsNVPTX.def

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TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX61)) TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX61))
TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX61)) TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX61))
TARGET_BUILTIN(__hmma_m8n32k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX61)) TARGET_BUILTIN(__hmma_m8n32k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX61))
// Builtins to support integer and sub-integer WMMA instructions on sm_72/sm_75 // Builtins to support integer and sub-integer WMMA instructions on sm_72/sm_75
TARGET_BUILTIN(__bmma_m8n8k128_ld_a_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63)) TARGET_BUILTIN(__bmma_m8n8k128_ld_a_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63))
TARGET_BUILTIN(__bmma_m8n8k128_ld_b_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63)) TARGET_BUILTIN(__bmma_m8n8k128_ld_b_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63))
TARGET_BUILTIN(__bmma_m8n8k128_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63)) TARGET_BUILTIN(__bmma_m8n8k128_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63))
TARGET_BUILTIN(__bmma_m8n8k128_mma_and_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_75,PTX71)) TARGET_BUILTIN(__bmma_m8n8k128_mma_and_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_80,PTX71))
TARGET_BUILTIN(__bmma_m8n8k128_mma_xor_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_75,PTX63)) TARGET_BUILTIN(__bmma_m8n8k128_mma_xor_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_75,PTX63))
TARGET_BUILTIN(__bmma_m8n8k128_st_c_i32, "vi*iC*UiIi", "", AND(SM_75,PTX63)) TARGET_BUILTIN(__bmma_m8n8k128_st_c_i32, "vi*iC*UiIi", "", AND(SM_75,PTX63))
TARGET_BUILTIN(__imma_m16n16k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) TARGET_BUILTIN(__imma_m16n16k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
TARGET_BUILTIN(__imma_m16n16k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) TARGET_BUILTIN(__imma_m16n16k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
TARGET_BUILTIN(__imma_m16n16k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) TARGET_BUILTIN(__imma_m16n16k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
TARGET_BUILTIN(__imma_m16n16k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) TARGET_BUILTIN(__imma_m16n16k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63))
TARGET_BUILTIN(__imma_m16n16k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63)) TARGET_BUILTIN(__imma_m16n16k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63))
TARGET_BUILTIN(__imma_m16n16k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) TARGET_BUILTIN(__imma_m16n16k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63))
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