[WebAssembly] Improve codegen for v128.bitselect

[tlively]

Summary

Add patterns selecting ((v1 ^ v2) & c) ^ v2 and ((v1 ^ v2) & ~c) ^ v2 to
v128.bitselect.

Resolves #56827.

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

def : Pat<(vec.vt (int_wasm_bitselect
           (BITSELECT $v1, $v2, $c)>;
 
 // Bitselect is equivalent to (c & v1) | (~c & v2)
 foreach vec = IntVecs in
 def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
             (and (vnot V128:$c), (vec.vt V128:$v2)))),
           (BITSELECT $v1, $v2, $c)>;
 
+// Bitselect is also equivalent to ((v1 ^ v2) & c) ^ v2
+foreach vec = IntVecs in
+def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
+                            (vec.vt V128:$c)),
+                       (vec.vt V128:$v2))),
+          (BITSELECT $v1, $v2, $c)>;
+
+// Same pattern with `c` negated so `a` and `b` get swapped.
+foreach vec = IntVecs in
+def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
+                            (vnot (vec.vt V128:$c))),
+                       (vec.vt V128:$v2))),
+          (BITSELECT $v2, $v1, $c)>;
+
 // Also implement vselect in terms of bitselect
 foreach vec = AllVecs in
 def : Pat<(vec.vt (vselect
             (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
           (BITSELECT $v1, $v2, $c)>;
 
 // MVP select on v128 values
 defm SELECT_V128 :

llvm/test/CodeGen/WebAssembly/simd-arith.ll

define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
   %inv_mask = xor <16 x i8> %c,
     <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
      i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %masked_v2 = and <16 x i8> %inv_mask, %v2
   %a = or <16 x i8> %masked_v1, %masked_v2
   ret <16 x i8> %a
 }
 
+; CHECK-LABEL: bitselect_xor_v16i8:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_v16i8 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <16 x i8> @bitselect_xor_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
+ %xor1 = xor <16 x i8> %v1, %v2
+ %and = and <16 x i8> %xor1, %c
+ %a = xor <16 x i8> %and, %v2
+ ret <16 x i8> %a
+}
+
+; CHECK-LABEL: bitselect_xor_reversed_v16i8:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_reversed_v16i8 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $1, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.not
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <16 x i8> @bitselect_xor_reversed_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
+ %xor1 = xor <16 x i8> %v1, %v2
+ %notc = xor <16 x i8> %c, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                            i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %and = and <16 x i8> %xor1, %notc
+ %a = xor <16 x i8> %and, %v2
+ ret <16 x i8> %a
+}
+
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_v8i16:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128-NEXT: .functype add_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
   %inv_mask = xor <8 x i16>
     <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>,
     %c
   %masked_v2 = and <8 x i16> %v2, %inv_mask
   %a = or <8 x i16> %masked_v1, %masked_v2
   ret <8 x i16> %a
 }
 
+; CHECK-LABEL: bitselect_xor_v8i16:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_v8i16 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <8 x i16> @bitselect_xor_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
+ %xor1 = xor <8 x i16> %v1, %v2
+ %and = and <8 x i16> %xor1, %c
+ %a = xor <8 x i16> %and, %v2
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: bitselect_xor_reversed_v8i16:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_reversed_v8i16 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $1, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.not
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <8 x i16> @bitselect_xor_reversed_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
+ %xor1 = xor <8 x i16> %v1, %v2
+ %notc = xor <8 x i16> %c, <i16 -1, i16 -1, i16 -1, i16 -1,
+                            i16 -1, i16 -1, i16 -1, i16 -1>
+ %and = and <8 x i16> %xor1, %notc
+ %a = xor <8 x i16> %and, %v2
+ ret <8 x i16> %a
+}
+
 ; CHECK-LABEL: extmul_low_s_v8i16:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %v1, <16 x i8> %v2) {
   %low1 = shufflevector <16 x i8> %v1, <16 x i8> undef,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>

 define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
   %masked_v1 = and <4 x i32> %c, %v1
   %inv_mask = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %c
   %masked_v2 = and <4 x i32> %inv_mask, %v2
   %a = or <4 x i32> %masked_v2, %masked_v1
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: bitselect_xor_v4i32:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_v4i32 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <4 x i32> @bitselect_xor_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
+ %xor1 = xor <4 x i32> %v1, %v2
+ %and = and <4 x i32> %xor1, %c
+ %a = xor <4 x i32> %and, %v2
+ ret <4 x i32> %a
+}
+
+; CHECK-LABEL: bitselect_xor_reversed_v4i32:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_reversed_v4i32 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $1, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.not
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <4 x i32> @bitselect_xor_reversed_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
+ %xor1 = xor <4 x i32> %v1, %v2
+ %notc = xor <4 x i32> %c, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %and = and <4 x i32> %xor1, %notc
+ %a = xor <4 x i32> %and, %v2
+ ret <4 x i32> %a
+}
+
 ; CHECK-LABEL: extmul_low_s_v4i32:
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %v1, <8 x i16> %v2) {
   %low1 = shufflevector <8 x i16> %v1, <8 x i16> undef,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>

 define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
   %masked_v1 = and <2 x i64> %v1, %c
   %inv_mask = xor <2 x i64> <i64 -1, i64 -1>, %c
   %masked_v2 = and <2 x i64> %v2, %inv_mask
   %a = or <2 x i64> %masked_v2, %masked_v1
   ret <2 x i64> %a
 }
 
+; CHECK-LABEL: bitselect_xor_v2i64:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_v2i64 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <2 x i64> @bitselect_xor_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
+ %xor1 = xor <2 x i64> %v1, %v2
+ %and = and <2 x i64> %xor1, %c
+ %a = xor <2 x i64> %and, %v2
+ ret <2 x i64> %a
+}
+
+; CHECK-LABEL: bitselect_xor_reversed_v2i64:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype bitselect_xor_reversed_v2i64 (v128, v128, v128) -> (v128){{$}}
+; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $1, $0{{$}}
+; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
+; SIMD128-FAST-NEXT: v128.xor
+; SIMD128-FAST-NEXT: v128.not
+; SIMD128-FAST-NEXT: v128.and
+; SIMD128-FAST-NEXT: v128.xor
+define <2 x i64> @bitselect_xor_reversed_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
+ %xor1 = xor <2 x i64> %v1, %v2
+ %notc = xor <2 x i64> %c, <i64 -1, i64 -1>
+ %and = and <2 x i64> %xor1, %notc
+ %a = xor <2 x i64> %and, %v2
+ ret <2 x i64> %a
+}
+
 ; CHECK-LABEL: extmul_low_s_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %v1, <4 x i32> %v2) {
   %low1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
   %low2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 0, i32 1>