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Differential D130654

[AMDGPU] Consider S_SETPRIO a scheduling boundary
ClosedPublic

Authored by rampitec on Jul 27 2022, 11:34 AM.

Details

Reviewers
kerbowa
foad
Commits
rG68901fdbebb7: [AMDGPU] Consider S_SETPRIO a scheduling boundary
Summary

The instruction is used to modify wave priority with the intent
to affect VALU execution and currently we can reschedule VALU
around it since that VALU does not have side effects.

Diff Detail

Unit TestsFailed

TimeTest
60,070 msx64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp
60,020 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,030 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test
60,030 msx64 debian > libFuzzer.libFuzzer::out-of-process-fuzz.test
60,030 msx64 debian > libFuzzer.libFuzzer::value-profile-load.test
View Full Test Results (76 Failed)

Event Timeline

rampitec created this revision.Jul 27 2022, 11:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 27 2022, 11:34 AM
Herald added subscribers: kosarev, jsilvanus, foad and 9 others. · View Herald Transcript
rampitec requested review of this revision.Jul 27 2022, 11:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 27 2022, 11:34 AM
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foad accepted this revision.Jul 27 2022, 11:47 AM

Seems reasonable!

This revision is now accepted and ready to land.Jul 27 2022, 11:47 AM
This revision was landed with ongoing or failed builds.Jul 27 2022, 11:50 AM
Closed by commit rG68901fdbebb7: [AMDGPU] Consider S_SETPRIO a scheduling boundary (authored by rampitec). · Explain Why
This revision was automatically updated to reflect the committed changes.
rampitec added a commit: rG68901fdbebb7: [AMDGPU] Consider S_SETPRIO a scheduling boundary.
Harbormaster completed remote builds in B177909: Diff 448108.Jul 27 2022, 12:28 PM
kerbowa added a comment.Jul 27 2022, 1:23 PM

Why not make it a scheduling boundary?

kerbowa added a comment.Jul 27 2022, 1:24 PM
In D130654#3683352, @kerbowa wrote:

Why not make it a scheduling boundary?

NVM misread the patch.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
1 line
test/
CodeGen/
AMDGPU/
4 lines

Diff 448108

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,483 Lines • ▼ Show 20 Lines if (MI.getOpcode() == AMDGPU::SCHED_BARRIER && MI.getOperand(0).getImm() == 0)
return true; return true;
// Target-independent instructions do not have an implicit-use of EXEC, even // Target-independent instructions do not have an implicit-use of EXEC, even
// when they operate on VGPRs. Treating EXEC modifications as scheduling // when they operate on VGPRs. Treating EXEC modifications as scheduling
// boundaries prevents incorrect movements of such instructions. // boundaries prevents incorrect movements of such instructions.
return MI.modifiesRegister(AMDGPU::EXEC, &RI) || return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 || MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
MI.getOpcode() == AMDGPU::S_SETREG_B32 || MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
MI.getOpcode() == AMDGPU::S_SETPRIO ||
changesVGPRIndexingMode(MI); changesVGPRIndexingMode(MI);
} }
bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const { bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
return Opcode == AMDGPU::DS_ORDERED_COUNT || return Opcode == AMDGPU::DS_ORDERED_COUNT ||
Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_INIT ||
Opcode == AMDGPU::DS_GWS_SEMA_V || Opcode == AMDGPU::DS_GWS_SEMA_V ||
Opcode == AMDGPU::DS_GWS_SEMA_BR || Opcode == AMDGPU::DS_GWS_SEMA_BR ||
▲ Show 20 Lines • Show All 4,994 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sched-setprio.ll

; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
declare void @llvm.amdgcn.s.setprio(i16) declare void @llvm.amdgcn.s.setprio(i16)
declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32) declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
; FIXME: setprio shall surround mfma instructions
; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32: ; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32:
; GCN: s_setprio 1 ; GCN: s_setprio 1
; GCN: s_setprio 0
; GCN: v_mfma ; GCN: v_mfma
; GCN: v_mfma ; GCN: v_mfma
; GCN: s_setprio 0
define amdgpu_kernel void @test_mfma_f32_4x4x1f32(<4 x float> addrspace(1)* %arg) #0 { define amdgpu_kernel void @test_mfma_f32_4x4x1f32(<4 x float> addrspace(1)* %arg) #0 {
bb: bb:
%in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg %in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
call void @llvm.amdgcn.s.setprio(i16 1) call void @llvm.amdgcn.s.setprio(i16 1)
%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 2.0, <4 x float> %in.1, i32 0, i32 0, i32 0) %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 2.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
%mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 3.0, float 4.0, <4 x float> %mai.1, i32 0, i32 0, i32 0) %mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 3.0, float 4.0, <4 x float> %mai.1, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.s.setprio(i16 0) call void @llvm.amdgcn.s.setprio(i16 0)
store <4 x float> %mai.2, <4 x float> addrspace(1)* %arg store <4 x float> %mai.2, <4 x float> addrspace(1)* %arg
ret void ret void
} }