[AMDGPU] Consider S_SETPRIO a scheduling boundary

[rampitec]

Summary

The instruction is used to modify wave priority with the intent
to affect VALU execution and currently we can reschedule VALU
around it since that VALU does not have side effects.

[foad]

Seems reasonable!

[kerbowa]

Why not make it a scheduling boundary?

[kerbowa]

In D130654#3683352, @kerbowa wrote:

Why not make it a scheduling boundary?

NVM misread the patch.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (MI.getOpcode() == AMDGPU::SCHED_BARRIER && MI.getOperand(0).getImm() == 0)
     return true;
 
   // Target-independent instructions do not have an implicit-use of EXEC, even
   // when they operate on VGPRs. Treating EXEC modifications as scheduling
   // boundaries prevents incorrect movements of such instructions.
   return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
          MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
          MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
+         MI.getOpcode() == AMDGPU::S_SETPRIO ||
          changesVGPRIndexingMode(MI);
 }
 
 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
   return Opcode == AMDGPU::DS_ORDERED_COUNT ||
          Opcode == AMDGPU::DS_GWS_INIT ||
          Opcode == AMDGPU::DS_GWS_SEMA_V ||
          Opcode == AMDGPU::DS_GWS_SEMA_BR ||

llvm/test/CodeGen/AMDGPU/sched-setprio.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
 
 declare void @llvm.amdgcn.s.setprio(i16)
 declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
 
-; FIXME: setprio shall surround mfma instructions
-
 ; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32:
 ; GCN: s_setprio 1
-; GCN: s_setprio 0
 ; GCN: v_mfma
 ; GCN: v_mfma
+; GCN: s_setprio 0
 define amdgpu_kernel void @test_mfma_f32_4x4x1f32(<4 x float> addrspace(1)* %arg) #0 {
 bb:
   %in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
   call void @llvm.amdgcn.s.setprio(i16 1)
   %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 2.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
   %mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 3.0, float 4.0, <4 x float> %mai.1, i32 0, i32 0, i32 0)
   call void @llvm.amdgcn.s.setprio(i16 0)
   store <4 x float> %mai.2, <4 x float> addrspace(1)* %arg
   ret void
 }