[IR] Don't treat callbr as indirect terminator

[nikic]

Summary

Callbr is no longer an indirect terminator in the sense that is relevant here (that it's successors cannot be updated). The primary effect of this change is that callbr no longer prevents formation of loop simplify form.

I decided to drop the isIndirectTerminator() method entirely and replace it with isa<IndirectBrInst>() checks. I assume this method was added to abstract over indirectbr and callbr, but it never really caught on, and there is nothing left to abstract anymore at this point.

[efriedma]

LGTM

[nickdesaulniers]

Patch LGTM; just running it through testing now.

[nickdesaulniers]

@nathanchance is also doing some testing, please wait for his green light before landing.

[nathanchance]

My Linux kernel build and QEMU boot tests (minus i386, due to an unrelated regression in mainline) showed no regressions with this change.

llvm/include/llvm/Analysis/SparsePropagation.h

if (!C || !isa<ConstantInt>(C)) {
       return;
     }
 
     // Constant condition variables mean the branch can only go a single way
     Succs[C->isNullValue()] = true;
     return;
   }
 
-  if (TI.isExceptionalTerminator() ||
-      TI.isIndirectTerminator()) {
+  if (!isa<SwitchInst>(TI)) {
+    // Unknown termintor, assume all successors are feasible.
     Succs.assign(Succs.size(), true);
     return;
   }
 
   SwitchInst &SI = cast<SwitchInst>(TI);
   LatticeVal SCValue;
   if (AggressiveUndef)
     SCValue = getValueState(KeyInfo::getLatticeKeyFromValue(SI.getCondition()));

llvm/include/llvm/IR/Instruction.h

public:
   bool isExceptionalTerminator() const {
     return isExceptionalTerminator(getOpcode());
   }
 
   /// It checks if this instruction is the only user of at least one of
   /// its operands.
   bool isOnlyUserOfAnyOperand();
 
-  bool isIndirectTerminator() const {
-    return isIndirectTerminator(getOpcode());
-  }
-
   static const char* getOpcodeName(unsigned OpCode);
 
   static inline bool isTerminator(unsigned OpCode) {
     return OpCode >= TermOpsBegin && OpCode < TermOpsEnd;
   }
 
   static inline bool isUnaryOp(unsigned Opcode) {
     return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
static inline bool isExceptionalTerminator(unsigned OpCode) {
     case Instruction::Invoke:
     case Instruction::Resume:
       return true;
     default:
       return false;
     }
   }
 
-  /// Returns true if the OpCode is a terminator with indirect targets.
-  static inline bool isIndirectTerminator(unsigned OpCode) {
-    switch (OpCode) {
-    case Instruction::IndirectBr:
-    case Instruction::CallBr:
-      return true;
-    default:
-      return false;
-    }
-  }
-
   //===--------------------------------------------------------------------===//
   // Metadata manipulation.
   //===--------------------------------------------------------------------===//
 
   /// Return true if this instruction has any metadata attached to it.
   bool hasMetadata() const { return DbgLoc || Value::hasMetadata(); }
 
   /// Return true if this instruction has metadata attached to it other than a

llvm/lib/Transforms/Utils/LoopRotationUtils.cpp

if (!isa<ConstantInt>(PHBI->getCondition()) ||
       // nested loops, causing both of the edges to now be critical and need to
       // be split.
       SmallVector<BasicBlock *, 4> ExitPreds(predecessors(Exit));
       bool SplitLatchEdge = false;
       for (BasicBlock *ExitPred : ExitPreds) {
         // We only need to split loop exit edges.
         Loop *PredLoop = LI->getLoopFor(ExitPred);
         if (!PredLoop || PredLoop->contains(Exit) ||
-            ExitPred->getTerminator()->isIndirectTerminator())
+            isa<IndirectBrInst>(ExitPred->getTerminator()))
           continue;
         SplitLatchEdge |= L->getLoopLatch() == ExitPred;
         BasicBlock *ExitSplit = SplitCriticalEdge(
                                                   ExitPred, Exit,
                                                   CriticalEdgeSplittingOptions(DT, LI, MSSAU).setPreserveLCSSA());
         ExitSplit->moveBefore(Exit);
       }
       assert(SplitLatchEdge &&

llvm/lib/Transforms/Utils/LoopSimplify.cpp

BasicBlock *llvm::InsertPreheaderForLoop(Loop *L, DominatorTree *DT,
 
   // Compute the set of predecessors of the loop that are not in the loop.
   SmallVector<BasicBlock*, 8> OutsideBlocks;
   for (BasicBlock *P : predecessors(Header)) {
     if (!L->contains(P)) {         // Coming in from outside the loop?
       // If the loop is branched to from an indirect terminator, we won't
       // be able to fully transform the loop, because it prohibits
       // edge splitting.
-      if (P->getTerminator()->isIndirectTerminator())
+      if (isa<IndirectBrInst>(P->getTerminator()))
         return nullptr;
 
       // Keep track of it.
       OutsideBlocks.push_back(P);
     }
   }
 
   // Split out the loop pre-header.
static Loop *separateNestedLoop(Loop *L, BasicBlock *Preheader,
   // Pull out all predecessors that have varying values in the loop.  This
   // handles the case when a PHI node has multiple instances of itself as
   // arguments.
   SmallVector<BasicBlock*, 8> OuterLoopPreds;
   for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
     if (PN->getIncomingValue(i) != PN ||
         !L->contains(PN->getIncomingBlock(i))) {
       // We can't split indirect control flow edges.
-      if (PN->getIncomingBlock(i)->getTerminator()->isIndirectTerminator())
+      if (isa<IndirectBrInst>(PN->getIncomingBlock(i)->getTerminator()))
         return nullptr;
       OuterLoopPreds.push_back(PN->getIncomingBlock(i));
     }
   }
   LLVM_DEBUG(dbgs() << "LoopSimplify: Splitting out a new outer loop\n");
 
   // If ScalarEvolution is around and knows anything about values in
   // this loop, tell it to forget them, because we're about to
static BasicBlock *insertUniqueBackedgeBlock(Loop *L, BasicBlock *Preheader,
 
   // The header is not an EH pad; preheader insertion should ensure this.
   assert(!Header->isEHPad() && "Can't insert backedge to EH pad");
 
   // Figure out which basic blocks contain back-edges to the loop header.
   std::vector<BasicBlock*> BackedgeBlocks;
   for (BasicBlock *P : predecessors(Header)) {
     // Indirect edges cannot be split, so we must fail if we find one.
-    if (P->getTerminator()->isIndirectTerminator())
+    if (isa<IndirectBrInst>(P->getTerminator()))
       return nullptr;
 
     if (P != Preheader) BackedgeBlocks.push_back(P);
   }
 
   // Create and insert the new backedge block...
   BasicBlock *BEBlock = BasicBlock::Create(Header->getContext(),
                                            Header->getName() + ".backedge", F);

llvm/test/Transforms/LoopDeletion/two-predecessors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -loop-deletion -S | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux-gnu"
 
 define dso_local i32 @hoge() local_unnamed_addr #0 {
 ; CHECK-LABEL: @hoge(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    callbr void asm sideeffect "", "!i"()
-; CHECK-NEXT:    to label [[BB1:%.*]] [label %bb2]
+; CHECK-NEXT:    to label [[BB1:%.*]] [label %bb2.preheader]
 ; CHECK:       bb1:
+; CHECK-NEXT:    br label [[BB2_PREHEADER:%.*]]
+; CHECK:       bb2.preheader:
 ; CHECK-NEXT:    br label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[TMP:%.*]] = phi i32 [ undef, [[BB1]] ], [ [[TMP3:%.*]], [[BB2]] ], [ undef, [[BB:%.*]] ]
+; CHECK-NEXT:    [[TMP:%.*]] = phi i32 [ [[TMP3:%.*]], [[BB2]] ], [ undef, [[BB2_PREHEADER]] ]
 ; CHECK-NEXT:    [[TMP3]] = tail call i32 bitcast (i32 (...)* @widget to i32 (i32)*)(i32 [[TMP]])
 ; CHECK-NEXT:    br label [[BB2]]
 ;
 bb:
   callbr void asm sideeffect "", "!i"() #1
   to label %bb1 [label %bb2]
 
 bb1:                                              ; preds = %bb

llvm/test/Transforms/LoopRotate/callbr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -S -loop-rotate -o - -verify-loop-info -verify-dom-info | FileCheck %s
 
 @d = external global i64, align 8
 @f = external global i32, align 4
 @g = external global i32, align 4
 @i = external global i32, align 4
 @h = external global i32, align 4
 
 define i32 @o() #0 {
 ; CHECK-LABEL: @o(
 ; CHECK-NEXT:    [[TMP1:%.*]] = alloca [1 x i32], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = load i8*, i8** bitcast (i64* @d to i8**), align 8
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* @f, align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
-; CHECK-NEXT:    br i1 [[TMP4]], label [[TMP17:%.*]], label [[DOTLR_PH2:%.*]]
-; CHECK:       .lr.ph2:
+; CHECK-NEXT:    br i1 [[TMP4]], label [[TMP17:%.*]], label [[DOTLR_PH4:%.*]]
+; CHECK:       .lr.ph4:
 ; CHECK-NEXT:    br label [[TMP5:%.*]]
-; CHECK:         [[TMP6:%.*]] = phi i32 [ [[TMP3]], [[DOTLR_PH2]] ], [ [[TMP15:%.*]], [[M_EXIT:%.*]] ]
+; CHECK:       5:
+; CHECK-NEXT:    [[TMP6:%.*]] = phi i32 [ [[TMP3]], [[DOTLR_PH4]] ], [ [[TMP15:%.*]], [[M_EXIT:%.*]] ]
 ; CHECK-NEXT:    [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 4
 ; CHECK-NEXT:    [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
 ; CHECK-NEXT:    store i32 [[TMP8]], i32* @g, align 4
 ; CHECK-NEXT:    [[TMP9:%.*]] = bitcast [1 x i32]* [[TMP1]] to i8*
 ; CHECK-NEXT:    [[TMP10:%.*]] = call i32 @n(i8* nonnull [[TMP9]], i8* [[TMP2]])
 ; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
 ; CHECK-NEXT:    br i1 [[TMP11]], label [[THREAD_PRE_SPLIT:%.*]], label [[DOT_CRIT_EDGE:%.*]]
 ; CHECK:       thread-pre-split:
 ; CHECK-NEXT:    [[DOTPR:%.*]] = load i32, i32* @i, align 4
 ; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[DOTPR]], 0
 ; CHECK-NEXT:    br i1 [[TMP12]], label [[M_EXIT]], label [[DOTLR_PH:%.*]]
 ; CHECK:       .lr.ph:
 ; CHECK-NEXT:    br label [[TMP13:%.*]]
-; CHECK:         [[DOT11:%.*]] = phi i32 [ undef, [[DOTLR_PH]] ], [ [[TMP14:%.*]], [[J_EXIT_I:%.*]] ]
-; CHECK-NEXT:    callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"() #1
-; CHECK-NEXT:    to label [[J_EXIT_I]] [label %m.exit]
+; CHECK:       13:
+; CHECK-NEXT:    [[DOT11:%.*]] = phi i32 [ undef, [[DOTLR_PH]] ], [ [[TMP14:%.*]], [[J_EXIT_I:%.*]] ]
+; CHECK-NEXT:    callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"() #[[ATTR1:[0-9]+]]
+; CHECK-NEXT:    to label [[J_EXIT_I]] [label %.m.exit_crit_edge]
 ; CHECK:       j.exit.i:
-; CHECK-NEXT:    [[TMP14]] = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #2
-; CHECK-NEXT:    br i1 [[TMP12]], label [[DOTM_EXIT_CRIT_EDGE:%.*]], label [[TMP13]]
+; CHECK-NEXT:    [[TMP14]] = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #[[ATTR2:[0-9]+]]
+; CHECK-NEXT:    br i1 [[TMP12]], label [[DOTM_EXIT_CRIT_EDGE2:%.*]], label [[TMP13]]
 ; CHECK:       .m.exit_crit_edge:
-; CHECK-NEXT:    [[SPLIT:%.*]] = phi i32 [ [[TMP14]], [[J_EXIT_I]] ]
+; CHECK-NEXT:    [[SPLIT:%.*]] = phi i32 [ [[DOT11]], [[TMP13]] ]
+; CHECK-NEXT:    br label [[M_EXIT]]
+; CHECK:       .m.exit_crit_edge2:
+; CHECK-NEXT:    [[SPLIT3:%.*]] = phi i32 [ [[TMP14]], [[J_EXIT_I]] ]
 ; CHECK-NEXT:    br label [[M_EXIT]]
 ; CHECK:       m.exit:
-; CHECK-NEXT:    [[DOT1_LCSSA:%.*]] = phi i32 [ [[DOT11]], [[TMP13]] ], [ [[SPLIT]], [[DOTM_EXIT_CRIT_EDGE]] ], [ undef, [[THREAD_PRE_SPLIT]] ]
+; CHECK-NEXT:    [[DOT1_LCSSA:%.*]] = phi i32 [ [[SPLIT]], [[DOTM_EXIT_CRIT_EDGE:%.*]] ], [ [[SPLIT3]], [[DOTM_EXIT_CRIT_EDGE2]] ], [ undef, [[THREAD_PRE_SPLIT]] ]
 ; CHECK-NEXT:    store i32 [[DOT1_LCSSA]], i32* @h, align 4
 ; CHECK-NEXT:    [[TMP15]] = load i32, i32* @f, align 4
 ; CHECK-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
-; CHECK-NEXT:    br i1 [[TMP16]], label [[DOT_CRIT_EDGE3:%.*]], label [[TMP5]]
+; CHECK-NEXT:    br i1 [[TMP16]], label [[DOT_CRIT_EDGE5:%.*]], label [[TMP5]]
 ; CHECK:       ._crit_edge:
 ; CHECK-NEXT:    br label [[TMP17]]
-; CHECK:       ._crit_edge3:
+; CHECK:       ._crit_edge5:
 ; CHECK-NEXT:    br label [[TMP17]]
-; CHECK:         ret i32 undef
+; CHECK:       17:
+; CHECK-NEXT:    ret i32 undef
 ;
   %1 = alloca [1 x i32], align 4
   %2 = load i8*, i8** bitcast (i64* @d to i8**), align 8
   br label %3
 
 ; <label>:3:                                      ; preds = %m.exit, %0
   %4 = load i32, i32* @f, align 4
   %5 = icmp eq i32 %4, 0