Adds support for splitting complex vectors so they can fit within vector registers
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Looks like I messed up my git-fu somewhere in preparing these patches. There are a few cleanup changes in this patch that should've been in a previous one. I'll try and clean that up when addressing other comments.
Can we do the splitting on the Target side of the boundary? So it gets asked to create a "v8f32 vcmul" from two values and generates a series for "extract-subvector; vcmul; insert-subvector" each of size v4i32. I don't think the pass/graph would actually need to change, it would just be up to the backend to generate something equivalent. Then the graph in simpler, and all the added shuffles would optimize away.
See lowerInterleavedLoad (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/ARM/ARMISelLowering.cpp#L21400) and lowerInterleavedStore (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/ARM/ARMISelLowering.cpp#L21548) for examples of that.
This was pushed over to be the responsibility of the target. Therefore this approach is no longer relevant.