[SCEVExpander] Use IRBuilder to create BinOp

[nikic]

Summary

This makes InsertBinOp in SCEVExpander go through the IRBuilder, which will fold the operation with InstSimplifyFolder. When doing this, it's important that the flags are directly passed to the builder, not fixed up after the fact, because it might have folded to some unrelated instruction. Expose a CreateNoWrapBinOp API for this purpose.

I am somewhat uncertain whether this change is actually desirable though. This does fold things as expected, but I'm not sure it's wanted in the LSR case, e.g. because it can shift a use from iv.inc to iv. Any thoughts on that?

[reames]

Unfortunately, I do think the LSR changes are problematic. I suspect this may break assumptions in LSR about register liveness in hard to predict ways. e.g. LoopStrengthReduce/X86/pr46943.ll undoes an optimization to reduce live ranges. (Though, why that particular example wasn't killed by RLEV I have no idea.)

You could make this conditional on LSRMode. You could have two builders, one simplifying and one not. Note sure if that's worth your while or not though.

[nikic]

Yeah, I think I'm going to drop this for now. What would probably make most sense to me is that the caller of SCEVExpander can provide the builder, so that different users can use different configurations. But that would need some IRBuilder API changes, because we'd still want to use a custom inserter in either case.

llvm/include/llvm/IR/IRBuilder.h

public:
   UnreachableInst *CreateUnreachable() {
     return Insert(new UnreachableInst(Context));
   }
 
   //===--------------------------------------------------------------------===//
   // Instruction creation methods: Binary Operators
   //===--------------------------------------------------------------------===//
 private:
-  BinaryOperator *CreateInsertNUWNSWBinOp(BinaryOperator::BinaryOps Opc,
-                                          Value *LHS, Value *RHS,
-                                          const Twine &Name,
-                                          bool HasNUW, bool HasNSW) {
-    BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name);
-    if (HasNUW) BO->setHasNoUnsignedWrap();
-    if (HasNSW) BO->setHasNoSignedWrap();
-    return BO;
-  }
-
   Instruction *setFPAttrs(Instruction *I, MDNode *FPMD,
                           FastMathFlags FMF) const {
     if (!FPMD)
       FPMD = DefaultFPMathTag;
     if (FPMD)
       I->setMetadata(LLVMContext::MD_fpmath, FPMD);
     I->setFastMathFlags(FMF);
     return I;
Value *getConstrainedFPPredicate(CmpInst::Predicate Predicate) {
     auto *PredicateMDS = MDString::get(Context, PredicateStr);
 
     return MetadataAsValue::get(Context, PredicateMDS);
   }
 
 public:
   Value *CreateAdd(Value *LHS, Value *RHS, const Twine &Name = "",
                    bool HasNUW = false, bool HasNSW = false) {
-    if (Value *V =
-            Folder.FoldNoWrapBinOp(Instruction::Add, LHS, RHS, HasNUW, HasNSW))
-      return V;
-    return CreateInsertNUWNSWBinOp(Instruction::Add, LHS, RHS, Name, HasNUW,
-                                   HasNSW);
+    return CreateNoWrapBinOp(Instruction::Add, LHS, RHS, HasNUW, HasNSW, Name);
   }
 
   Value *CreateNSWAdd(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateAdd(LHS, RHS, Name, false, true);
   }
 
   Value *CreateNUWAdd(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateAdd(LHS, RHS, Name, true, false);
   }
 
   Value *CreateSub(Value *LHS, Value *RHS, const Twine &Name = "",
                    bool HasNUW = false, bool HasNSW = false) {
-    if (Value *V =
-            Folder.FoldNoWrapBinOp(Instruction::Sub, LHS, RHS, HasNUW, HasNSW))
-      return V;
-    return CreateInsertNUWNSWBinOp(Instruction::Sub, LHS, RHS, Name, HasNUW,
-                                   HasNSW);
+    return CreateNoWrapBinOp(Instruction::Sub, LHS, RHS, HasNUW, HasNSW, Name);
   }
 
   Value *CreateNSWSub(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateSub(LHS, RHS, Name, false, true);
   }
 
   Value *CreateNUWSub(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateSub(LHS, RHS, Name, true, false);
   }
 
   Value *CreateMul(Value *LHS, Value *RHS, const Twine &Name = "",
                    bool HasNUW = false, bool HasNSW = false) {
-    if (Value *V =
-            Folder.FoldNoWrapBinOp(Instruction::Mul, LHS, RHS, HasNUW, HasNSW))
-      return V;
-    return CreateInsertNUWNSWBinOp(Instruction::Mul, LHS, RHS, Name, HasNUW,
-                                   HasNSW);
+    return CreateNoWrapBinOp(Instruction::Mul, LHS, RHS, HasNUW, HasNSW, Name);
   }
 
   Value *CreateNSWMul(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateMul(LHS, RHS, Name, false, true);
   }
 
   Value *CreateNUWMul(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateMul(LHS, RHS, Name, true, false);
public:
   Value *CreateSRem(Value *LHS, Value *RHS, const Twine &Name = "") {
     if (Value *V = Folder.FoldBinOp(Instruction::SRem, LHS, RHS))
       return V;
     return Insert(BinaryOperator::CreateSRem(LHS, RHS), Name);
   }
 
   Value *CreateShl(Value *LHS, Value *RHS, const Twine &Name = "",
                    bool HasNUW = false, bool HasNSW = false) {
-    if (Value *V =
-            Folder.FoldNoWrapBinOp(Instruction::Shl, LHS, RHS, HasNUW, HasNSW))
-      return V;
-    return CreateInsertNUWNSWBinOp(Instruction::Shl, LHS, RHS, Name,
-                                   HasNUW, HasNSW);
+    return CreateNoWrapBinOp(Instruction::Shl, LHS, RHS, HasNUW, HasNSW, Name);
   }
 
   Value *CreateShl(Value *LHS, const APInt &RHS, const Twine &Name = "",
                    bool HasNUW = false, bool HasNSW = false) {
     return CreateShl(LHS, ConstantInt::get(LHS->getType(), RHS), Name,
                      HasNUW, HasNSW);
   }
 
Value *CreateBinOp(Instruction::BinaryOps Opc,
                      MDNode *FPMathTag = nullptr) {
     if (Value *V = Folder.FoldBinOp(Opc, LHS, RHS)) return V;
     Instruction *BinOp = BinaryOperator::Create(Opc, LHS, RHS);
     if (isa<FPMathOperator>(BinOp))
       setFPAttrs(BinOp, FPMathTag, FMF);
     return Insert(BinOp, Name);
   }
 
+  Value *CreateNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS,
+                           bool HasNUW, bool HasNSW, const Twine &Name = "") {
+    if (Value *V = Folder.FoldNoWrapBinOp(Opc, LHS, RHS, HasNUW, HasNSW))
+      return V;
+
+    BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name);
+    if (HasNUW)
+      BO->setHasNoUnsignedWrap();
+    if (HasNSW)
+      BO->setHasNoSignedWrap();
+    return BO;
+  }
+
   Value *CreateLogicalAnd(Value *Cond1, Value *Cond2, const Twine &Name = "") {
     assert(Cond2->getType()->isIntOrIntVectorTy(1));
     return CreateSelect(Cond1, Cond2,
                         ConstantInt::getNullValue(Cond2->getType()), Name);
   }
 
   Value *CreateLogicalOr(Value *Cond1, Value *Cond2, const Twine &Name = "") {
     assert(Cond2->getType()->isIntOrIntVectorTy(1));

llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp

while (const Loop *L = SE.LI.getLoopFor(Builder.GetInsertBlock())) {
       if (!Preheader) break;
 
       // Ok, move up a level.
       Builder.SetInsertPoint(Preheader->getTerminator());
     }
   }
 
   // If we haven't found this binop, insert it.
-  // TODO: Use the Builder, which will make CreateBinOp below fold with
-  // InstSimplifyFolder.
-  Instruction *BO = Builder.Insert(BinaryOperator::Create(Opcode, LHS, RHS));
-  BO->setDebugLoc(Loc);
-  if (Flags & SCEV::FlagNUW)
-    BO->setHasNoUnsignedWrap();
-  if (Flags & SCEV::FlagNSW)
-    BO->setHasNoSignedWrap();
-
+  Value *BO = Builder.CreateNoWrapBinOp(Opcode, LHS, RHS, Flags & SCEV::FlagNUW,
+                                        Flags & SCEV::FlagNSW);
+  if (auto *I = dyn_cast<Instruction>(BO))
+    I->setDebugLoc(Loc);
   return BO;
 }
 
 /// FactorOutConstant - Test if S is divisible by Factor, using signed
 /// division. If so, update S with Factor divided out and return true.
 /// S need not be evenly divisible if a reasonable remainder can be
 /// computed.
 static bool FactorOutConstant(const SCEV *&S, const SCEV *&Remainder,

llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll

 exit:
   store i32 %offset, i32* %res
   ret void
 }
 
 define void @cbz_exit_minsize(i32* %in, i32* %res) #0 {
 ; CHECK-LABEL: cbz_exit_minsize:
 ; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    movs r2, #0
 ; CHECK-NEXT:  .LBB3_1: @ %loop
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldr.w r3, [r0, r2, lsl #2]
+; CHECK-NEXT:    ldr.w r4, [r0, r2, lsl #2]
+; CHECK-NEXT:    mov r3, r2
 ; CHECK-NEXT:    adds r2, #1
-; CHECK-NEXT:    cmp r3, #0
+; CHECK-NEXT:    cmp r4, #0
 ; CHECK-NEXT:    bne .LBB3_1
 ; CHECK-NEXT:  @ %bb.2: @ %exit
-; CHECK-NEXT:    subs r0, r2, #1
-; CHECK-NEXT:    str r0, [r1]
-; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    str r3, [r1]
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   br label %loop
 
 loop:
   %offset = phi i32 [ 0, %entry ], [ %next, %loop ]
   %ptr = getelementptr i32, i32* %in, i32 %offset
   %val = load i32, i32* %ptr
   %next = add i32 %offset, 1
   %cmp = icmp eq i32 %val, 0
   br i1 %cmp, label %exit, label %loop
 
 exit:
   store i32 %offset, i32* %res
   ret void
 }
 
 define void @cbnz_exit_minsize(i32* %in, i32* %res) #0 {
 ; CHECK-LABEL: cbnz_exit_minsize:
 ; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    movs r2, #0
 ; CHECK-NEXT:  .LBB4_1: @ %loop
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldr.w r3, [r0, r2, lsl #2]
+; CHECK-NEXT:    ldr.w r4, [r0, r2, lsl #2]
+; CHECK-NEXT:    mov r3, r2
 ; CHECK-NEXT:    adds r2, #1
-; CHECK-NEXT:    cmp r3, #0
+; CHECK-NEXT:    cmp r4, #0
 ; CHECK-NEXT:    beq .LBB4_1
 ; CHECK-NEXT:  @ %bb.2: @ %exit
-; CHECK-NEXT:    subs r0, r2, #1
-; CHECK-NEXT:    str r0, [r1]
-; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    str r3, [r1]
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   br label %loop
 
 loop:
   %offset = phi i32 [ 0, %entry ], [ %next, %loop ]
   %ptr = getelementptr i32, i32* %in, i32 %offset
   %val = load i32, i32* %ptr
   %next = add i32 %offset, 1

llvm/test/CodeGen/X86/break-false-dep.ll

 ; SSE-LINUX-NEXT:    #NO_APP
 ; SSE-LINUX-NEXT:    #APP
 ; SSE-LINUX-NEXT:    #NO_APP
 ; SSE-LINUX-NEXT:    #APP
 ; SSE-LINUX-NEXT:    #NO_APP
 ; SSE-LINUX-NEXT:    #APP
 ; SSE-LINUX-NEXT:    #NO_APP
 ; SSE-LINUX-NEXT:    movl $1, %r8d
-; SSE-LINUX-NEXT:    xorl %ecx, %ecx
+; SSE-LINUX-NEXT:    xorl %r9d, %r9d
 ; SSE-LINUX-NEXT:    .p2align 4, 0x90
 ; SSE-LINUX-NEXT:  .LBB13_1: # %inner_loop
 ; SSE-LINUX-NEXT:    # =>This Inner Loop Header: Depth=1
-; SSE-LINUX-NEXT:    movq %rcx, %rax
-; SSE-LINUX-NEXT:    shrq $6, %rcx
-; SSE-LINUX-NEXT:    movq (%rsi,%rcx,8), %rcx
-; SSE-LINUX-NEXT:    btq %rax, %rcx
-; SSE-LINUX-NEXT:    leaq 1(%rax), %rcx
+; SSE-LINUX-NEXT:    movq %r9, %rcx
+; SSE-LINUX-NEXT:    movq %r9, %rax
+; SSE-LINUX-NEXT:    shrq $6, %rax
+; SSE-LINUX-NEXT:    movq (%rsi,%rax,8), %rax
+; SSE-LINUX-NEXT:    incq %r9
+; SSE-LINUX-NEXT:    btq %rcx, %rax
 ; SSE-LINUX-NEXT:    jae .LBB13_1
 ; SSE-LINUX-NEXT:  # %bb.2: # %loop_end
 ; SSE-LINUX-NEXT:    # in Loop: Header=BB13_1 Depth=1
-; SSE-LINUX-NEXT:    leaq 1(%r8), %r9
+; SSE-LINUX-NEXT:    leaq 1(%r8), %rax
 ; SSE-LINUX-NEXT:    xorps %xmm4, %xmm4
-; SSE-LINUX-NEXT:    cvtsi2sd %r9, %xmm4
+; SSE-LINUX-NEXT:    cvtsi2sd %rax, %xmm4
 ; SSE-LINUX-NEXT:    movapd %xmm0, %xmm5
 ; SSE-LINUX-NEXT:    subsd %xmm4, %xmm5
 ; SSE-LINUX-NEXT:    mulsd %xmm1, %xmm5
-; SSE-LINUX-NEXT:    leaq -1(%rcx), %rax
 ; SSE-LINUX-NEXT:    xorps %xmm4, %xmm4
-; SSE-LINUX-NEXT:    cvtsi2sd %rax, %xmm4
+; SSE-LINUX-NEXT:    cvtsi2sd %rcx, %xmm4
 ; SSE-LINUX-NEXT:    mulsd %xmm2, %xmm4
 ; SSE-LINUX-NEXT:    addsd %xmm5, %xmm4
 ; SSE-LINUX-NEXT:    divsd %xmm3, %xmm4
 ; SSE-LINUX-NEXT:    movsd %xmm4, -8(%rdi,%r8,8)
-; SSE-LINUX-NEXT:    movq %r9, %r8
-; SSE-LINUX-NEXT:    cmpq %r9, %rdx
+; SSE-LINUX-NEXT:    movq %rax, %r8
+; SSE-LINUX-NEXT:    cmpq %rax, %rdx
 ; SSE-LINUX-NEXT:    jge .LBB13_1
 ; SSE-LINUX-NEXT:  # %bb.3: # %loopdone
 ; SSE-LINUX-NEXT:    retq
 ;
 ; SSE-WIN-LABEL: loopclearance2:
 ; SSE-WIN:       # %bb.0: # %entry
 ; SSE-WIN-NEXT:    subq $152, %rsp
 ; SSE-WIN-NEXT:    .seh_stackalloc 152

 ; SSE-WIN-NEXT:    #NO_APP
 ; SSE-WIN-NEXT:    #APP
 ; SSE-WIN-NEXT:    #NO_APP
 ; SSE-WIN-NEXT:    #APP
 ; SSE-WIN-NEXT:    #NO_APP
 ; SSE-WIN-NEXT:    #APP
 ; SSE-WIN-NEXT:    #NO_APP
 ; SSE-WIN-NEXT:    movl $1, %r9d
-; SSE-WIN-NEXT:    xorl %r11d, %r11d
+; SSE-WIN-NEXT:    xorl %r10d, %r10d
 ; SSE-WIN-NEXT:    .p2align 4, 0x90
 ; SSE-WIN-NEXT:  .LBB13_1: # %inner_loop
 ; SSE-WIN-NEXT:    # =>This Inner Loop Header: Depth=1
-; SSE-WIN-NEXT:    movq %r11, %r10
-; SSE-WIN-NEXT:    movq %r11, %rax
+; SSE-WIN-NEXT:    movq %r10, %r11
+; SSE-WIN-NEXT:    movq %r10, %rax
 ; SSE-WIN-NEXT:    shrq $6, %rax
 ; SSE-WIN-NEXT:    movq (%rdx,%rax,8), %rax
+; SSE-WIN-NEXT:    incq %r10
 ; SSE-WIN-NEXT:    btq %r11, %rax
-; SSE-WIN-NEXT:    leaq 1(%r11), %r11
 ; SSE-WIN-NEXT:    jae .LBB13_1
 ; SSE-WIN-NEXT:  # %bb.2: # %loop_end
 ; SSE-WIN-NEXT:    # in Loop: Header=BB13_1 Depth=1
-; SSE-WIN-NEXT:    leaq 1(%r9), %r10
+; SSE-WIN-NEXT:    leaq 1(%r9), %rax
 ; SSE-WIN-NEXT:    xorps %xmm4, %xmm4
-; SSE-WIN-NEXT:    cvtsi2sd %r10, %xmm4
+; SSE-WIN-NEXT:    cvtsi2sd %rax, %xmm4
 ; SSE-WIN-NEXT:    movapd %xmm2, %xmm5
 ; SSE-WIN-NEXT:    subsd %xmm4, %xmm5
 ; SSE-WIN-NEXT:    mulsd %xmm3, %xmm5
-; SSE-WIN-NEXT:    leaq -1(%r11), %rax
 ; SSE-WIN-NEXT:    xorps %xmm4, %xmm4
-; SSE-WIN-NEXT:    cvtsi2sd %rax, %xmm4
+; SSE-WIN-NEXT:    cvtsi2sd %r11, %xmm4
 ; SSE-WIN-NEXT:    mulsd %xmm1, %xmm4
 ; SSE-WIN-NEXT:    addsd %xmm5, %xmm4
 ; SSE-WIN-NEXT:    divsd %xmm0, %xmm4
 ; SSE-WIN-NEXT:    movsd %xmm4, -8(%rcx,%r9,8)
-; SSE-WIN-NEXT:    movq %r10, %r9
-; SSE-WIN-NEXT:    cmpq %r10, %r8
+; SSE-WIN-NEXT:    movq %rax, %r9
+; SSE-WIN-NEXT:    cmpq %rax, %r8
 ; SSE-WIN-NEXT:    jge .LBB13_1
 ; SSE-WIN-NEXT:  # %bb.3: # %loopdone
 ; SSE-WIN-NEXT:    movaps (%rsp), %xmm7 # 16-byte Reload
 ; SSE-WIN-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
 ; SSE-WIN-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
 ; SSE-WIN-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
 ; SSE-WIN-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Reload
 ; SSE-WIN-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm12 # 16-byte Reload

 ; AVX1-NEXT:    #NO_APP
 ; AVX1-NEXT:    #APP
 ; AVX1-NEXT:    #NO_APP
 ; AVX1-NEXT:    #APP
 ; AVX1-NEXT:    #NO_APP
 ; AVX1-NEXT:    #APP
 ; AVX1-NEXT:    #NO_APP
 ; AVX1-NEXT:    movl $1, %r9d
-; AVX1-NEXT:    xorl %r11d, %r11d
+; AVX1-NEXT:    xorl %r10d, %r10d
 ; AVX1-NEXT:    .p2align 4, 0x90
 ; AVX1-NEXT:  .LBB13_1: # %inner_loop
 ; AVX1-NEXT:    # =>This Inner Loop Header: Depth=1
-; AVX1-NEXT:    movq %r11, %r10
-; AVX1-NEXT:    movq %r11, %rax
+; AVX1-NEXT:    movq %r10, %r11
+; AVX1-NEXT:    movq %r10, %rax
 ; AVX1-NEXT:    shrq $6, %rax
 ; AVX1-NEXT:    movq (%rdx,%rax,8), %rax
+; AVX1-NEXT:    incq %r10
 ; AVX1-NEXT:    btq %r11, %rax
-; AVX1-NEXT:    leaq 1(%r11), %r11
 ; AVX1-NEXT:    jae .LBB13_1
 ; AVX1-NEXT:  # %bb.2: # %loop_end
 ; AVX1-NEXT:    # in Loop: Header=BB13_1 Depth=1
-; AVX1-NEXT:    leaq 1(%r9), %r10
-; AVX1-NEXT:    vcvtsi2sd %r10, %xmm6, %xmm4
+; AVX1-NEXT:    leaq 1(%r9), %rax
+; AVX1-NEXT:    vcvtsi2sd %rax, %xmm6, %xmm4
 ; AVX1-NEXT:    vsubsd %xmm4, %xmm2, %xmm4
 ; AVX1-NEXT:    vmulsd %xmm3, %xmm4, %xmm4
-; AVX1-NEXT:    leaq -1(%r11), %rax
-; AVX1-NEXT:    vcvtsi2sd %rax, %xmm6, %xmm5
+; AVX1-NEXT:    vcvtsi2sd %r11, %xmm6, %xmm5
 ; AVX1-NEXT:    vmulsd %xmm1, %xmm5, %xmm5
 ; AVX1-NEXT:    vaddsd %xmm5, %xmm4, %xmm4
 ; AVX1-NEXT:    vdivsd %xmm0, %xmm4, %xmm4
 ; AVX1-NEXT:    vmovsd %xmm4, -8(%rcx,%r9,8)
-; AVX1-NEXT:    movq %r10, %r9
-; AVX1-NEXT:    cmpq %r10, %r8
+; AVX1-NEXT:    movq %rax, %r9
+; AVX1-NEXT:    cmpq %rax, %r8
 ; AVX1-NEXT:    jge .LBB13_1
 ; AVX1-NEXT:  # %bb.3: # %loopdone
 ; AVX1-NEXT:    vmovaps (%rsp), %xmm7 # 16-byte Reload
 ; AVX1-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
 ; AVX1-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
 ; AVX1-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
 ; AVX1-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Reload
 ; AVX1-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm12 # 16-byte Reload

 ; AVX512VL-NEXT:    #NO_APP
 ; AVX512VL-NEXT:    #APP
 ; AVX512VL-NEXT:    #NO_APP
 ; AVX512VL-NEXT:    #APP
 ; AVX512VL-NEXT:    #NO_APP
 ; AVX512VL-NEXT:    #APP
 ; AVX512VL-NEXT:    #NO_APP
 ; AVX512VL-NEXT:    movl $1, %r9d
-; AVX512VL-NEXT:    xorl %r11d, %r11d
+; AVX512VL-NEXT:    xorl %r10d, %r10d
 ; AVX512VL-NEXT:    .p2align 4, 0x90
 ; AVX512VL-NEXT:  .LBB13_1: # %inner_loop
 ; AVX512VL-NEXT:    # =>This Inner Loop Header: Depth=1
-; AVX512VL-NEXT:    movq %r11, %r10
-; AVX512VL-NEXT:    movq %r11, %rax
+; AVX512VL-NEXT:    movq %r10, %r11
+; AVX512VL-NEXT:    movq %r10, %rax
 ; AVX512VL-NEXT:    shrq $6, %rax
 ; AVX512VL-NEXT:    movq (%rdx,%rax,8), %rax
+; AVX512VL-NEXT:    incq %r10
 ; AVX512VL-NEXT:    btq %r11, %rax
-; AVX512VL-NEXT:    leaq 1(%r11), %r11
 ; AVX512VL-NEXT:    jae .LBB13_1
 ; AVX512VL-NEXT:  # %bb.2: # %loop_end
 ; AVX512VL-NEXT:    # in Loop: Header=BB13_1 Depth=1
-; AVX512VL-NEXT:    leaq 1(%r9), %r10
-; AVX512VL-NEXT:    vcvtsi2sd %r10, %xmm6, %xmm4
+; AVX512VL-NEXT:    leaq 1(%r9), %rax
+; AVX512VL-NEXT:    vcvtsi2sd %rax, %xmm6, %xmm4
 ; AVX512VL-NEXT:    vsubsd %xmm4, %xmm2, %xmm4
 ; AVX512VL-NEXT:    vmulsd %xmm3, %xmm4, %xmm4
-; AVX512VL-NEXT:    leaq -1(%r11), %rax
-; AVX512VL-NEXT:    vcvtsi2sd %rax, %xmm6, %xmm5
+; AVX512VL-NEXT:    vcvtsi2sd %r11, %xmm6, %xmm5
 ; AVX512VL-NEXT:    vmulsd %xmm1, %xmm5, %xmm5
 ; AVX512VL-NEXT:    vaddsd %xmm5, %xmm4, %xmm4
 ; AVX512VL-NEXT:    vdivsd %xmm0, %xmm4, %xmm4
 ; AVX512VL-NEXT:    vmovsd %xmm4, -8(%rcx,%r9,8)
-; AVX512VL-NEXT:    movq %r10, %r9
-; AVX512VL-NEXT:    cmpq %r10, %r8
+; AVX512VL-NEXT:    movq %rax, %r9
+; AVX512VL-NEXT:    cmpq %rax, %r8
 ; AVX512VL-NEXT:    jge .LBB13_1
 ; AVX512VL-NEXT:  # %bb.3: # %loopdone
 ; AVX512VL-NEXT:    vmovaps (%rsp), %xmm7 # 16-byte Reload
 ; AVX512VL-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
 ; AVX512VL-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
 ; AVX512VL-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
 ; AVX512VL-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Reload
 ; AVX512VL-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm12 # 16-byte Reload

llvm/test/Transforms/LoopDeletion/pr53969.ll

 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
 ; CHECK-NEXT:    br i1 [[TMP10]], label [[BB33_LOOPEXIT1:%.*]], label [[BB34_PREHEADER:%.*]]
 ; CHECK:       bb34.preheader:
 ; CHECK-NEXT:    br label [[BB34:%.*]]
 ; CHECK:       bb11:
 ; CHECK-NEXT:    [[TMP2_LCSSA12:%.*]] = phi i32 [ 11, [[BB34]] ]
 ; CHECK-NEXT:    br label [[BB33_LOOPEXIT:%.*]]
 ; CHECK:       bb12:
-; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[TMP40:%.*]], 0
 ; CHECK-NEXT:    br label [[BB14:%.*]]
 ; CHECK:       bb14:
 ; CHECK-NEXT:    br i1 true, label [[BB32:%.*]], label [[BB22:%.*]]
 ; CHECK:       bb22:
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 4 to i32
-; CHECK-NEXT:    [[TMP23:%.*]] = or i32 [[TMP1]], undef
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc i64 4 to i32
+; CHECK-NEXT:    [[TMP23:%.*]] = or i32 [[TMP0]], undef
 ; CHECK-NEXT:    [[TMP24:%.*]] = add i32 [[TMP23]], undef
 ; CHECK-NEXT:    br i1 false, label [[BB42:%.*]], label [[BB25:%.*]]
 ; CHECK:       bb25:
 ; CHECK-NEXT:    br label [[BB31:%.*]]
 ; CHECK:       bb31:
 ; CHECK-NEXT:    unreachable
 ; CHECK:       bb32:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb33.loopexit:
 ; CHECK-NEXT:    [[TMP2_LCSSA9:%.*]] = phi i32 [ [[TMP2_LCSSA12]], [[BB11:%.*]] ]
 ; CHECK-NEXT:    br label [[BB33:%.*]]
 ; CHECK:       bb33.loopexit1:
 ; CHECK-NEXT:    [[TMP2_LCSSA:%.*]] = phi i32 [ [[TMP2]], [[BB1]] ]
 ; CHECK-NEXT:    br label [[BB33]]
 ; CHECK:       bb33:
 ; CHECK-NEXT:    [[TMP210:%.*]] = phi i32 [ [[TMP2_LCSSA]], [[BB33_LOOPEXIT1]] ], [ [[TMP2_LCSSA9]], [[BB33_LOOPEXIT]] ]
 ; CHECK-NEXT:    call void @use(i32 [[TMP210]])
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb34:
 ; CHECK-NEXT:    [[TMP36:%.*]] = xor i32 0, [[TMP8]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = add i32 [[TMP36]], undef
 ; CHECK-NEXT:    [[TMP39:%.*]] = add i32 [[TMP38]], undef
-; CHECK-NEXT:    [[TMP40]] = sext i32 [[TMP39]] to i64
+; CHECK-NEXT:    [[TMP40:%.*]] = sext i32 [[TMP39]] to i64
 ; CHECK-NEXT:    br i1 false, label [[BB11]], label [[BB12:%.*]]
 ; CHECK:       bb42:
 ; CHECK-NEXT:    [[TMP24_LCSSA:%.*]] = phi i32 [ [[TMP24]], [[BB22]] ]
-; CHECK-NEXT:    [[TMP18_LCSSA4:%.*]] = phi i64 [ [[TMP0]], [[BB22]] ]
+; CHECK-NEXT:    [[TMP18_LCSSA4:%.*]] = phi i64 [ [[TMP40]], [[BB22]] ]
 ; CHECK-NEXT:    store atomic i64 [[TMP18_LCSSA4]], i64 addrspace(1)* undef unordered, align 8
 ; CHECK-NEXT:    call void @use(i32 [[TMP24_LCSSA]])
 ; CHECK-NEXT:    ret void
 ;
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb31, %bb

llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll

 ; CHECK-LABEL: sqlite3DropTriggerPtr:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    pushq %rbx
 ; CHECK-NEXT:    movl $1, %ebx
 ; CHECK-NEXT:    callq check@PLT
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movq %rbx, %rcx
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    je .LBB0_4
+; CHECK-NEXT:    je .LBB0_3
 ; CHECK-NEXT:  # %bb.2: # %bb4
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
-; CHECK-NEXT:    incq %rbx
+; CHECK-NEXT:    leaq 1(%rcx), %rbx
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    jne .LBB0_1
-; CHECK-NEXT:  # %bb.3: # %bb8split
-; CHECK-NEXT:    decq %rbx
-; CHECK-NEXT:  .LBB0_4: # %bb8
-; CHECK-NEXT:    movq %rbx, %rax
+; CHECK-NEXT:  .LBB0_3: # %bb8
+; CHECK-NEXT:    movq %rcx, %rax
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
 bb:
   %cmp = call zeroext i1 @check()
   br label %bb1
 
 bb1:                                              ; preds = %bb4, %bb
   %t0 = phi i64 [ 0, %bb ], [ %t3, %bb4 ]

llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll

 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
 ; CHECK-NEXT:    call void @use(i8 zeroext [[IV]])
 ; CHECK-NEXT:    [[IV_NEXT]] = add i8 [[IV]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[TMP0:%.*]] = add i8 [[IV_NEXT]], -1
-; CHECK-NEXT:    ret i8 [[TMP0]]
+; CHECK-NEXT:    ret i8 [[IV]]
 ;
 entry:
   br label %loop
 
 loop:
   %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]
   call void @use(i8 zeroext %iv)
 

 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i8 [ 127, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
 ; CHECK-NEXT:    call void @use(i8 zeroext [[IV]])
 ; CHECK-NEXT:    [[IV_NEXT]] = add i8 [[IV]], -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], 127
 ; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[TMP0:%.*]] = add i8 [[IV_NEXT]], 1
-; CHECK-NEXT:    ret i8 [[TMP0]]
+; CHECK-NEXT:    ret i8 [[IV]]
 ;
 entry:
   br label %loop
 
 loop:
   %iv = phi i8 [ 127, %entry ], [ %iv.next, %loop ]
   call void @use(i8 zeroext %iv)
 

 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
 ; CHECK-NEXT:    call void @use(i8 zeroext [[IV]])
 ; CHECK-NEXT:    [[IV_NEXT]] = add nuw i8 [[IV]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], -1
 ; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[TMP0:%.*]] = add i8 [[IV_NEXT]], -1
-; CHECK-NEXT:    ret i8 [[TMP0]]
+; CHECK-NEXT:    ret i8 [[IV]]
 ;
 entry:
   br label %loop
 
 loop:
   %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]
   call void @use(i8 zeroext %iv)
 
   %iv.next = add nuw i8 %iv, 1
   %cmp = icmp eq i8 %iv.next, -1
   br i1 %cmp, label %exit, label %loop
 
 exit:
   ret i8 %iv
 }

llvm/test/Transforms/LoopStrengthReduce/depth-limit-overrun.ll

 ; DEFAULT-NEXT:    [[PHI4:%.*]] = phi i32 [ [[B:%.*]], [[ENTRY]] ], [ [[I35:%.*]], [[OUTER_TAIL]] ]
 ; DEFAULT-NEXT:    br label [[GUARD:%.*]]
 ; DEFAULT:       guard:
 ; DEFAULT-NEXT:    [[LCMP_MOD:%.*]] = icmp eq i32 [[C]], 0
 ; DEFAULT-NEXT:    br i1 [[LCMP_MOD]], label [[OUTER_TAIL]], label [[PREHEADER:%.*]]
 ; DEFAULT:       preheader:
 ; DEFAULT-NEXT:    [[I15:%.*]] = shl i32 [[B]], 1
 ; DEFAULT-NEXT:    [[TMP1:%.*]] = mul i32 [[PHI2]], -1
-; DEFAULT-NEXT:    [[TMP2:%.*]] = mul i32 [[TMP1]], -1
-; DEFAULT-NEXT:    [[TMP3:%.*]] = sub i32 [[PHI4]], [[TMP2]]
-; DEFAULT-NEXT:    [[TMP4:%.*]] = add i32 [[B]], [[PHI4]]
-; DEFAULT-NEXT:    [[TMP5:%.*]] = sub i32 [[TMP4]], [[TMP2]]
-; DEFAULT-NEXT:    [[TMP6:%.*]] = sub i32 14, [[TMP5]]
-; DEFAULT-NEXT:    [[TMP7:%.*]] = add i32 [[TMP0]], [[PHI2]]
+; DEFAULT-NEXT:    [[TMP2:%.*]] = sub i32 [[PHI4]], [[PHI2]]
+; DEFAULT-NEXT:    [[TMP3:%.*]] = add i32 [[B]], [[PHI4]]
+; DEFAULT-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP3]], [[PHI2]]
+; DEFAULT-NEXT:    [[TMP5:%.*]] = sub i32 14, [[TMP4]]
+; DEFAULT-NEXT:    [[TMP6:%.*]] = add i32 [[TMP0]], [[PHI2]]
 ; DEFAULT-NEXT:    br label [[INNER_LOOP:%.*]]
 ; DEFAULT:       inner_loop:
-; DEFAULT-NEXT:    [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP6]], [[PREHEADER]] ]
-; DEFAULT-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP5]], [[PREHEADER]] ]
-; DEFAULT-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP3]], [[PREHEADER]] ]
+; DEFAULT-NEXT:    [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP5]], [[PREHEADER]] ]
+; DEFAULT-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP4]], [[PREHEADER]] ]
+; DEFAULT-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP2]], [[PREHEADER]] ]
 ; DEFAULT-NEXT:    [[PHI5:%.*]] = phi i32 [ [[PHI3]], [[PREHEADER]] ], [ [[I30:%.*]], [[INNER_LOOP]] ]
 ; DEFAULT-NEXT:    [[PHI6:%.*]] = phi i32 [ [[PHI2]], [[PREHEADER]] ], [ [[I33:%.*]], [[INNER_LOOP]] ]
 ; DEFAULT-NEXT:    [[ITER:%.*]] = phi i32 [ [[C]], [[PREHEADER]] ], [ [[ITER_SUB:%.*]], [[INNER_LOOP]] ]
 ; DEFAULT-NEXT:    [[I17:%.*]] = sub i32 [[PHI4]], [[PHI6]]
 ; DEFAULT-NEXT:    [[I18:%.*]] = sub i32 14, [[PHI5]]
 ; DEFAULT-NEXT:    [[I19:%.*]] = mul i32 [[I18]], [[C]]
 ; DEFAULT-NEXT:    [[FACTOR_PROL:%.*]] = shl i32 [[PHI5]], 1
-; DEFAULT-NEXT:    [[TMP8:%.*]] = add i32 [[LSR_IV1]], [[I19]]
-; DEFAULT-NEXT:    [[TMP9:%.*]] = add i32 [[TMP8]], [[FACTOR_PROL]]
-; DEFAULT-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP9]], 1
-; DEFAULT-NEXT:    [[TMP11:%.*]] = add i32 [[LSR_IV]], [[TMP10]]
-; DEFAULT-NEXT:    [[TMP12:%.*]] = sub i32 [[LSR_IV3]], [[I19]]
-; DEFAULT-NEXT:    [[TMP13:%.*]] = sub i32 [[TMP12]], [[FACTOR_PROL]]
-; DEFAULT-NEXT:    [[TMP14:%.*]] = mul i32 [[C]], [[TMP13]]
-; DEFAULT-NEXT:    [[TMP15:%.*]] = add i32 [[LSR_IV1]], [[I19]]
-; DEFAULT-NEXT:    [[TMP16:%.*]] = add i32 [[TMP15]], [[FACTOR_PROL]]
-; DEFAULT-NEXT:    [[TMP17:%.*]] = shl i32 [[TMP16]], 1
-; DEFAULT-NEXT:    [[TMP18:%.*]] = add i32 [[TMP14]], [[TMP17]]
-; DEFAULT-NEXT:    [[TMP19:%.*]] = add i32 [[LSR_IV]], [[TMP18]]
-; DEFAULT-NEXT:    [[I29:%.*]] = mul i32 [[TMP11]], [[C]]
-; DEFAULT-NEXT:    [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP19]], 1
+; DEFAULT-NEXT:    [[TMP7:%.*]] = add i32 [[LSR_IV1]], [[I19]]
+; DEFAULT-NEXT:    [[TMP8:%.*]] = add i32 [[TMP7]], [[FACTOR_PROL]]
+; DEFAULT-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP8]], 1
+; DEFAULT-NEXT:    [[TMP10:%.*]] = add i32 [[LSR_IV]], [[TMP9]]
+; DEFAULT-NEXT:    [[TMP11:%.*]] = sub i32 [[LSR_IV3]], [[I19]]
+; DEFAULT-NEXT:    [[TMP12:%.*]] = sub i32 [[TMP11]], [[FACTOR_PROL]]
+; DEFAULT-NEXT:    [[TMP13:%.*]] = mul i32 [[C]], [[TMP12]]
+; DEFAULT-NEXT:    [[TMP14:%.*]] = add i32 [[LSR_IV1]], [[I19]]
+; DEFAULT-NEXT:    [[TMP15:%.*]] = add i32 [[TMP14]], [[FACTOR_PROL]]
+; DEFAULT-NEXT:    [[TMP16:%.*]] = shl i32 [[TMP15]], 1
+; DEFAULT-NEXT:    [[TMP17:%.*]] = add i32 [[TMP13]], [[TMP16]]
+; DEFAULT-NEXT:    [[TMP18:%.*]] = add i32 [[LSR_IV]], [[TMP17]]
+; DEFAULT-NEXT:    [[I29:%.*]] = mul i32 [[TMP10]], [[C]]
+; DEFAULT-NEXT:    [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP18]], 1
 ; DEFAULT-NEXT:    [[I30]] = add i32 [[I17]], [[FACTOR_2_PROL]]
 ; DEFAULT-NEXT:    [[I33]] = add i32 [[PHI6]], -3
 ; DEFAULT-NEXT:    [[ITER_SUB]] = add i32 [[ITER]], -1
 ; DEFAULT-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 3
 ; DEFAULT-NEXT:    [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 3
 ; DEFAULT-NEXT:    [[LSR_IV_NEXT4]] = add i32 [[LSR_IV3]], -3
 ; DEFAULT-NEXT:    [[ITER_CMP:%.*]] = icmp eq i32 [[ITER_SUB]], 0
 ; DEFAULT-NEXT:    br i1 [[ITER_CMP]], label [[OUTER_TAIL_LOOPEXIT:%.*]], label [[INNER_LOOP]]
 ; DEFAULT:       outer_tail.loopexit:
 ; DEFAULT-NEXT:    br label [[OUTER_TAIL]]
 ; DEFAULT:       outer_tail:
-; DEFAULT-NEXT:    [[PHI7:%.*]] = phi i32 [ [[PHI2]], [[GUARD]] ], [ [[TMP7]], [[OUTER_TAIL_LOOPEXIT]] ]
+; DEFAULT-NEXT:    [[PHI7:%.*]] = phi i32 [ [[PHI2]], [[GUARD]] ], [ [[TMP6]], [[OUTER_TAIL_LOOPEXIT]] ]
 ; DEFAULT-NEXT:    [[I35]] = sub i32 [[A]], [[PHI7]]
 ; DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[I35]], 9876
 ; DEFAULT-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[OUTER_LOOP]]
 ; DEFAULT:       exit:
 ; DEFAULT-NEXT:    ret void
 ;
 ; LIMIT-LABEL: @test(
 ; LIMIT-NEXT:  entry:
 ; LIMIT-NEXT:    br label [[OUTER_LOOP:%.*]]
 ; LIMIT:       outer_loop:
 ; LIMIT-NEXT:    [[PHI2:%.*]] = phi i32 [ [[A:%.*]], [[ENTRY:%.*]] ], [ 204, [[OUTER_TAIL:%.*]] ]
 ; LIMIT-NEXT:    [[PHI3:%.*]] = phi i32 [ [[A]], [[ENTRY]] ], [ 243, [[OUTER_TAIL]] ]
 ; LIMIT-NEXT:    [[PHI4:%.*]] = phi i32 [ [[B:%.*]], [[ENTRY]] ], [ [[I35:%.*]], [[OUTER_TAIL]] ]
 ; LIMIT-NEXT:    br label [[GUARD:%.*]]
 ; LIMIT:       guard:
 ; LIMIT-NEXT:    [[LCMP_MOD:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; LIMIT-NEXT:    br i1 [[LCMP_MOD]], label [[OUTER_TAIL]], label [[PREHEADER:%.*]]
 ; LIMIT:       preheader:
 ; LIMIT-NEXT:    [[I15:%.*]] = shl i32 [[B]], 1
 ; LIMIT-NEXT:    [[TMP0:%.*]] = mul i32 [[PHI2]], -1
-; LIMIT-NEXT:    [[TMP1:%.*]] = mul i32 [[TMP0]], -1
-; LIMIT-NEXT:    [[TMP2:%.*]] = sub i32 [[PHI4]], [[TMP1]]
-; LIMIT-NEXT:    [[TMP3:%.*]] = add i32 [[B]], [[PHI4]]
-; LIMIT-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP3]], [[TMP1]]
-; LIMIT-NEXT:    [[TMP5:%.*]] = sub i32 14, [[TMP4]]
+; LIMIT-NEXT:    [[TMP1:%.*]] = sub i32 [[PHI4]], [[PHI2]]
+; LIMIT-NEXT:    [[TMP2:%.*]] = add i32 [[B]], [[PHI4]]
+; LIMIT-NEXT:    [[TMP3:%.*]] = sub i32 [[TMP2]], [[PHI2]]
+; LIMIT-NEXT:    [[TMP4:%.*]] = sub i32 14, [[TMP3]]
 ; LIMIT-NEXT:    br label [[INNER_LOOP:%.*]]
 ; LIMIT:       inner_loop:
-; LIMIT-NEXT:    [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP5]], [[PREHEADER]] ]
-; LIMIT-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP4]], [[PREHEADER]] ]
-; LIMIT-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP2]], [[PREHEADER]] ]
+; LIMIT-NEXT:    [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[INNER_LOOP]] ], [ [[TMP4]], [[PREHEADER]] ]
+; LIMIT-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[INNER_LOOP]] ], [ [[TMP3]], [[PREHEADER]] ]
+; LIMIT-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[INNER_LOOP]] ], [ [[TMP1]], [[PREHEADER]] ]
 ; LIMIT-NEXT:    [[PHI5:%.*]] = phi i32 [ [[PHI3]], [[PREHEADER]] ], [ [[I30:%.*]], [[INNER_LOOP]] ]
 ; LIMIT-NEXT:    [[PHI6:%.*]] = phi i32 [ [[PHI2]], [[PREHEADER]] ], [ [[I33:%.*]], [[INNER_LOOP]] ]
 ; LIMIT-NEXT:    [[ITER:%.*]] = phi i32 [ [[C]], [[PREHEADER]] ], [ [[ITER_SUB:%.*]], [[INNER_LOOP]] ]
 ; LIMIT-NEXT:    [[I17:%.*]] = sub i32 [[PHI4]], [[PHI6]]
 ; LIMIT-NEXT:    [[I18:%.*]] = sub i32 14, [[PHI5]]
 ; LIMIT-NEXT:    [[I19:%.*]] = mul i32 [[I18]], [[C]]
 ; LIMIT-NEXT:    [[FACTOR_PROL:%.*]] = shl i32 [[PHI5]], 1
-; LIMIT-NEXT:    [[TMP6:%.*]] = add i32 [[LSR_IV1]], [[I19]]
-; LIMIT-NEXT:    [[TMP7:%.*]] = add i32 [[TMP6]], [[FACTOR_PROL]]
-; LIMIT-NEXT:    [[TMP8:%.*]] = shl i32 [[TMP7]], 1
-; LIMIT-NEXT:    [[TMP9:%.*]] = add i32 [[LSR_IV]], [[TMP8]]
-; LIMIT-NEXT:    [[TMP10:%.*]] = sub i32 [[LSR_IV3]], [[I19]]
-; LIMIT-NEXT:    [[TMP11:%.*]] = sub i32 [[TMP10]], [[FACTOR_PROL]]
-; LIMIT-NEXT:    [[TMP12:%.*]] = mul i32 [[C]], [[TMP11]]
-; LIMIT-NEXT:    [[TMP13:%.*]] = add i32 [[LSR_IV1]], [[I19]]
-; LIMIT-NEXT:    [[TMP14:%.*]] = add i32 [[TMP13]], [[FACTOR_PROL]]
-; LIMIT-NEXT:    [[TMP15:%.*]] = shl i32 [[TMP14]], 1
-; LIMIT-NEXT:    [[TMP16:%.*]] = add i32 [[TMP12]], [[TMP15]]
-; LIMIT-NEXT:    [[TMP17:%.*]] = add i32 [[LSR_IV]], [[TMP16]]
-; LIMIT-NEXT:    [[I29:%.*]] = mul i32 [[TMP9]], [[C]]
-; LIMIT-NEXT:    [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP17]], 1
+; LIMIT-NEXT:    [[TMP5:%.*]] = add i32 [[LSR_IV1]], [[I19]]
+; LIMIT-NEXT:    [[TMP6:%.*]] = add i32 [[TMP5]], [[FACTOR_PROL]]
+; LIMIT-NEXT:    [[TMP7:%.*]] = shl i32 [[TMP6]], 1
+; LIMIT-NEXT:    [[TMP8:%.*]] = add i32 [[LSR_IV]], [[TMP7]]
+; LIMIT-NEXT:    [[TMP9:%.*]] = sub i32 [[LSR_IV3]], [[I19]]
+; LIMIT-NEXT:    [[TMP10:%.*]] = sub i32 [[TMP9]], [[FACTOR_PROL]]
+; LIMIT-NEXT:    [[TMP11:%.*]] = mul i32 [[C]], [[TMP10]]
+; LIMIT-NEXT:    [[TMP12:%.*]] = add i32 [[LSR_IV1]], [[I19]]
+; LIMIT-NEXT:    [[TMP13:%.*]] = add i32 [[TMP12]], [[FACTOR_PROL]]
+; LIMIT-NEXT:    [[TMP14:%.*]] = shl i32 [[TMP13]], 1
+; LIMIT-NEXT:    [[TMP15:%.*]] = add i32 [[TMP11]], [[TMP14]]
+; LIMIT-NEXT:    [[TMP16:%.*]] = add i32 [[LSR_IV]], [[TMP15]]
+; LIMIT-NEXT:    [[I29:%.*]] = mul i32 [[TMP8]], [[C]]
+; LIMIT-NEXT:    [[FACTOR_2_PROL:%.*]] = shl i32 [[TMP16]], 1
 ; LIMIT-NEXT:    [[I30]] = add i32 [[I17]], [[FACTOR_2_PROL]]
 ; LIMIT-NEXT:    [[I33]] = add i32 [[PHI6]], -3
 ; LIMIT-NEXT:    [[ITER_SUB]] = add i32 [[ITER]], -1
 ; LIMIT-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 3
 ; LIMIT-NEXT:    [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 3
 ; LIMIT-NEXT:    [[LSR_IV_NEXT4]] = add i32 [[LSR_IV3]], -3
 ; LIMIT-NEXT:    [[ITER_CMP:%.*]] = icmp eq i32 [[ITER_SUB]], 0
 ; LIMIT-NEXT:    br i1 [[ITER_CMP]], label [[OUTER_TAIL_LOOPEXIT:%.*]], label [[INNER_LOOP]]

llvm/test/Transforms/LoopStrengthReduce/wrong-hoisting-iv.ll

 ; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32 addrspace(3)* undef, align 4
 ; CHECK-NEXT:    [[VAL1:%.*]] = add i32 undef, 12
 ; CHECK-NEXT:    [[VAL2:%.*]] = trunc i64 undef to i32
 ; CHECK-NEXT:    [[VAL3:%.*]] = mul i32 [[VAL1]], [[VAL2]]
 ; CHECK-NEXT:    [[VAL4:%.*]] = sub i32 [[VAL]], [[VAL3]]
 ; CHECK-NEXT:    [[VAL5:%.*]] = ashr i32 undef, undef
 ; CHECK-NEXT:    [[VAL6:%.*]] = sub i32 [[VAL4]], [[VAL5]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i32 [[VAL]], 7
-; CHECK-NEXT:    [[TMP1:%.*]] = mul i32 [[VAL3]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = mul i32 [[VAL5]], 7
 ; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 [[TMP0]], [[TMP1]]
-; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[VAL5]], 7
-; CHECK-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[VAL6]], 3
+; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[VAL6]], 3
 ; CHECK-NEXT:    br label [[BB7:%.*]]
 ; CHECK:       bb7:
 ; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB32:%.*]] ], [ 0, [[BB:%.*]] ]
 ; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB32]] ], [ -8, [[BB]] ]
 ; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 8
-; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add nuw nsw i32 [[LSR_IV1]], [[TMP5]]
+; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add nuw nsw i32 [[LSR_IV1]], [[TMP3]]
 ; CHECK-NEXT:    [[VAL10:%.*]] = icmp ult i64 [[LSR_IV_NEXT]], 65536
 ; CHECK-NEXT:    br i1 [[VAL10]], label [[BB12:%.*]], label [[BB11:%.*]]
 ; CHECK:       bb11:
 ; CHECK-NEXT:    unreachable
 ; CHECK:       bb12:
 ; CHECK-NEXT:    [[VAL14:%.*]] = icmp slt i32 undef, undef
 ; CHECK-NEXT:    br i1 [[VAL14]], label [[BB17:%.*]], label [[BB12_BB15SPLITSPLITSPLITSPLITSPLIT_CRIT_EDGE:%.*]]
 ; CHECK:       bb15splitsplitsplitsplitsplitsplit:
 ; CHECK-NEXT:    br label [[BB15SPLITSPLITSPLITSPLITSPLIT:%.*]]
 ; CHECK:       bb12.bb15splitsplitsplitsplitsplit_crit_edge:
-; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[VAL6]], [[LSR_IV1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[VAL6]], [[LSR_IV1]]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLITSPLITSPLITSPLIT]]
 ; CHECK:       bb15splitsplitsplitsplitsplit:
-; CHECK-NEXT:    [[VAL16_PH_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP6]], [[BB12_BB15SPLITSPLITSPLITSPLITSPLIT_CRIT_EDGE]] ], [ [[VAL35:%.*]], [[BB15SPLITSPLITSPLITSPLITSPLITSPLIT:%.*]] ]
+; CHECK-NEXT:    [[VAL16_PH_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP4]], [[BB12_BB15SPLITSPLITSPLITSPLITSPLIT_CRIT_EDGE]] ], [ [[VAL35:%.*]], [[BB15SPLITSPLITSPLITSPLITSPLITSPLIT:%.*]] ]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLITSPLITSPLIT:%.*]]
 ; CHECK:       bb17.bb15splitsplitsplitsplit_crit_edge:
-; CHECK-NEXT:    [[TMP7:%.*]] = shl i32 [[VAL]], 1
-; CHECK-NEXT:    [[TMP8:%.*]] = mul i32 [[VAL1]], [[VAL2]]
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP8]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = sub i32 [[TMP7]], [[TMP9]]
-; CHECK-NEXT:    [[TMP11:%.*]] = shl i32 [[VAL5]], 1
-; CHECK-NEXT:    [[TMP12:%.*]] = sub i32 [[TMP10]], [[TMP11]]
-; CHECK-NEXT:    [[TMP13:%.*]] = add i32 [[TMP12]], [[LSR_IV1]]
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[VAL]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[VAL1]], [[VAL2]]
+; CHECK-NEXT:    [[TMP7:%.*]] = shl i32 [[TMP6]], 1
+; CHECK-NEXT:    [[TMP8:%.*]] = sub i32 [[TMP5]], [[TMP7]]
+; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[VAL5]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = sub i32 [[TMP8]], [[TMP9]]
+; CHECK-NEXT:    [[TMP11:%.*]] = add i32 [[TMP10]], [[LSR_IV1]]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLITSPLITSPLIT]]
 ; CHECK:       bb15splitsplitsplitsplit:
-; CHECK-NEXT:    [[VAL16_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP13]], [[BB17_BB15SPLITSPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLITSPLIT]] ]
+; CHECK-NEXT:    [[VAL16_PH_PH_PH_PH:%.*]] = phi i32 [ [[TMP11]], [[BB17_BB15SPLITSPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLITSPLIT]] ]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLITSPLIT:%.*]]
 ; CHECK:       bb20.bb15splitsplitsplit_crit_edge:
-; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[VAL]], 3
-; CHECK-NEXT:    [[TMP15:%.*]] = mul i32 [[VAL1]], [[VAL2]]
-; CHECK-NEXT:    [[TMP16:%.*]] = mul i32 [[TMP15]], 3
-; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP14]], [[TMP16]]
-; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[VAL5]], 3
-; CHECK-NEXT:    [[TMP19:%.*]] = sub i32 [[TMP17]], [[TMP18]]
-; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP19]], [[LSR_IV1]]
+; CHECK-NEXT:    [[TMP12:%.*]] = mul i32 [[VAL]], 3
+; CHECK-NEXT:    [[TMP13:%.*]] = mul i32 [[VAL1]], [[VAL2]]
+; CHECK-NEXT:    [[TMP14:%.*]] = mul i32 [[VAL5]], 3
+; CHECK-NEXT:    [[TMP15:%.*]] = sub i32 [[TMP12]], [[TMP14]]
+; CHECK-NEXT:    [[TMP16:%.*]] = add i32 [[TMP15]], [[LSR_IV1]]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLITSPLIT]]
 ; CHECK:       bb15splitsplitsplit:
-; CHECK-NEXT:    [[VAL16_PH_PH_PH:%.*]] = phi i32 [ [[TMP20]], [[BB20_BB15SPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLIT]] ]
+; CHECK-NEXT:    [[VAL16_PH_PH_PH:%.*]] = phi i32 [ [[TMP16]], [[BB20_BB15SPLITSPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH_PH]], [[BB15SPLITSPLITSPLITSPLIT]] ]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLIT:%.*]]
 ; CHECK:       bb23.bb15splitsplit_crit_edge:
-; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[VAL]], 2
-; CHECK-NEXT:    [[TMP22:%.*]] = mul i32 [[VAL1]], [[VAL2]]
-; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 2
-; CHECK-NEXT:    [[TMP24:%.*]] = sub i32 [[TMP21]], [[TMP23]]
-; CHECK-NEXT:    [[TMP25:%.*]] = shl i32 [[VAL5]], 2
-; CHECK-NEXT:    [[TMP26:%.*]] = sub i32 [[TMP24]], [[TMP25]]
-; CHECK-NEXT:    [[TMP27:%.*]] = add i32 [[TMP26]], [[LSR_IV1]]
+; CHECK-NEXT:    [[TMP17:%.*]] = shl i32 [[VAL]], 2
+; CHECK-NEXT:    [[TMP18:%.*]] = mul i32 [[VAL1]], [[VAL2]]
+; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 2
+; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP17]], [[TMP19]]
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[VAL5]], 2
+; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP20]], [[TMP21]]
+; CHECK-NEXT:    [[TMP23:%.*]] = add i32 [[TMP22]], [[LSR_IV1]]
 ; CHECK-NEXT:    br label [[BB15SPLITSPLIT]]
 ; CHECK:       bb15splitsplit:
-; CHECK-NEXT:    [[VAL16_PH_PH:%.*]] = phi i32 [ [[TMP27]], [[BB23_BB15SPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH]], [[BB15SPLITSPLITSPLIT]] ]
+; CHECK-NEXT:    [[VAL16_PH_PH:%.*]] = phi i32 [ [[TMP23]], [[BB23_BB15SPLITSPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH_PH]], [[BB15SPLITSPLITSPLIT]] ]
 ; CHECK-NEXT:    br label [[BB15SPLIT:%.*]]
 ; CHECK:       bb26.bb15split_crit_edge:
-; CHECK-NEXT:    [[TMP28:%.*]] = mul i32 [[VAL]], 5
-; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[VAL1]], [[VAL2]]
-; CHECK-NEXT:    [[TMP30:%.*]] = mul i32 [[TMP29]], 5
-; CHECK-NEXT:    [[TMP31:%.*]] = sub i32 [[TMP28]], [[TMP30]]
-; CHECK-NEXT:    [[TMP32:%.*]] = mul i32 [[VAL5]], 5
-; CHECK-NEXT:    [[TMP33:%.*]] = sub i32 [[TMP31]], [[TMP32]]
-; CHECK-NEXT:    [[TMP34:%.*]] = add i32 [[TMP33]], [[LSR_IV1]]
+; CHECK-NEXT:    [[TMP24:%.*]] = mul i32 [[VAL]], 5
+; CHECK-NEXT:    [[TMP25:%.*]] = mul i32 [[VAL1]], [[VAL2]]
+; CHECK-NEXT:    [[TMP26:%.*]] = mul i32 [[VAL5]], 5
+; CHECK-NEXT:    [[TMP27:%.*]] = sub i32 [[TMP24]], [[TMP26]]
+; CHECK-NEXT:    [[TMP28:%.*]] = add i32 [[TMP27]], [[LSR_IV1]]
 ; CHECK-NEXT:    br label [[BB15SPLIT]]
 ; CHECK:       bb15split:
-; CHECK-NEXT:    [[VAL16_PH:%.*]] = phi i32 [ [[TMP34]], [[BB26_BB15SPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH]], [[BB15SPLITSPLIT]] ]
+; CHECK-NEXT:    [[VAL16_PH:%.*]] = phi i32 [ [[TMP28]], [[BB26_BB15SPLIT_CRIT_EDGE:%.*]] ], [ [[VAL16_PH_PH]], [[BB15SPLITSPLIT]] ]
 ; CHECK-NEXT:    br label [[BB15:%.*]]
 ; CHECK:       bb29.bb15_crit_edge:
-; CHECK-NEXT:    [[TMP35:%.*]] = mul i32 [[VAL]], 6
-; CHECK-NEXT:    [[TMP36:%.*]] = mul i32 [[VAL1]], [[VAL2]]
-; CHECK-NEXT:    [[TMP37:%.*]] = mul i32 [[TMP36]], 6
-; CHECK-NEXT:    [[TMP38:%.*]] = sub i32 [[TMP35]], [[TMP37]]
-; CHECK-NEXT:    [[TMP39:%.*]] = mul i32 [[VAL5]], 6
-; CHECK-NEXT:    [[TMP40:%.*]] = sub i32 [[TMP38]], [[TMP39]]
-; CHECK-NEXT:    [[TMP41:%.*]] = add i32 [[TMP40]], [[LSR_IV1]]
+; CHECK-NEXT:    [[TMP29:%.*]] = mul i32 [[VAL]], 6
+; CHECK-NEXT:    [[TMP30:%.*]] = mul i32 [[VAL1]], [[VAL2]]
+; CHECK-NEXT:    [[TMP31:%.*]] = mul i32 [[TMP30]], 6
+; CHECK-NEXT:    [[TMP32:%.*]] = sub i32 [[TMP29]], [[TMP31]]
+; CHECK-NEXT:    [[TMP33:%.*]] = mul i32 [[VAL5]], 6
+; CHECK-NEXT:    [[TMP34:%.*]] = sub i32 [[TMP32]], [[TMP33]]
+; CHECK-NEXT:    [[TMP35:%.*]] = add i32 [[TMP34]], [[LSR_IV1]]
 ; CHECK-NEXT:    br label [[BB15]]
 ; CHECK:       bb15:
-; CHECK-NEXT:    [[VAL16:%.*]] = phi i32 [ [[TMP41]], [[BB29_BB15_CRIT_EDGE:%.*]] ], [ [[VAL16_PH]], [[BB15SPLIT]] ]
+; CHECK-NEXT:    [[VAL16:%.*]] = phi i32 [ [[TMP35]], [[BB29_BB15_CRIT_EDGE:%.*]] ], [ [[VAL16_PH]], [[BB15SPLIT]] ]
 ; CHECK-NEXT:    call void @widget() [ "deopt"(i32 [[VAL16]], i32 3, i32 [[VAL]]) ]
 ; CHECK-NEXT:    unreachable
 ; CHECK:       bb17:
 ; CHECK-NEXT:    [[VAL19:%.*]] = icmp slt i32 undef, undef
 ; CHECK-NEXT:    br i1 [[VAL19]], label [[BB20:%.*]], label [[BB17_BB15SPLITSPLITSPLITSPLIT_CRIT_EDGE]]
 ; CHECK:       bb20:
 ; CHECK-NEXT:    [[VAL22:%.*]] = icmp slt i32 undef, undef
 ; CHECK-NEXT:    br i1 [[VAL22]], label [[BB23:%.*]], label [[BB20_BB15SPLITSPLITSPLIT_CRIT_EDGE]]
 ; CHECK:       bb23:
 ; CHECK-NEXT:    [[VAL25:%.*]] = icmp slt i32 undef, undef
 ; CHECK-NEXT:    br i1 [[VAL25]], label [[BB26:%.*]], label [[BB23_BB15SPLITSPLIT_CRIT_EDGE]]
 ; CHECK:       bb26:
 ; CHECK-NEXT:    [[VAL28:%.*]] = icmp slt i32 undef, undef
 ; CHECK-NEXT:    br i1 [[VAL28]], label [[BB29:%.*]], label [[BB26_BB15SPLIT_CRIT_EDGE]]
 ; CHECK:       bb29:
 ; CHECK-NEXT:    [[VAL31:%.*]] = icmp slt i32 undef, undef
 ; CHECK-NEXT:    br i1 [[VAL31]], label [[BB32]], label [[BB29_BB15_CRIT_EDGE]]
 ; CHECK:       bb32:
-; CHECK-NEXT:    [[TMP42:%.*]] = add i32 [[TMP4]], [[LSR_IV1]]
-; CHECK-NEXT:    [[VAL35]] = add i32 [[TMP42]], [[VAL6]]
+; CHECK-NEXT:    [[TMP36:%.*]] = add i32 [[TMP2]], [[LSR_IV1]]
+; CHECK-NEXT:    [[VAL35]] = add i32 [[TMP36]], [[VAL6]]
 ; CHECK-NEXT:    br i1 false, label [[BB7]], label [[BB15SPLITSPLITSPLITSPLITSPLITSPLIT]]
 ;
 bb:
   %val = load i32, i32 addrspace(3)* undef, align 4
   %val1 = add i32 undef, 12
   %val2 = trunc i64 undef to i32
   %val3 = mul i32 %val1, %val2
   %val4 = sub i32 %val, %val3