[LiveIntervals] Fix incorrect range (re)construction from subranges.

[dfukalov]

Summary

After D82916 updateAllRanges() started to fix holes in main range with
subranges but it fails on instructions with two subregs def which are parts of
one reg. The main range constructed with all subranges of subregs just after
processing the first operand. So the main range gets intervals from subranges
those are not updated yet.

The patch takes into account lane mask to update the main range.

[dfukalov]

LiveIntervals dumps for the test, before the patch:
Before first move:

%1 [16r,32r:0) 0@16r  L0000000000000003 [16r,32r:0) 0@16r  L000000000000000C [16r,32r:0) 0@16r  weight:0.000000e+00
%2 [32r,32d:0) 0@32r  weight:0.000000e+00
%3 [48r,64r:0)[64r,80r:1) 0@48r 1@64r  L0000000000000003 [48r,80r:0) 0@48r  L000000000000000C [64r,80r:0) 0@64r  weight:0.000000e+00
%4 [80r,80d:0) 0@80r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function func: NoPHIs

0B      bb.0:
16B       INLINEASM &"" [attdialect], $0:[regdef:VGPR_32], def undef %1.sub0:vreg_64, $1:[regdef:VGPR_32], def undef %1.sub1:vreg_64
32B       dead %2:vreg_64 = COPY %1:vreg_64
48B       undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
64B       %3.sub1:vreg_64 = COPY %3.sub0:vreg_64
80B       dead %4:vreg_64 = COPY %3:vreg_64

After the first move:

%1 [16r,72r:0) 0@16r  L0000000000000003 [16r,72r:0) 0@16r  L000000000000000C [16r,72r:0) 0@16r  weight:0.000000e+00
%2 [72r,72d:0) 0@72r  weight:0.000000e+00
%3 [48r,64r:0)[64r,80r:1) 0@48r 1@64r  L0000000000000003 [48r,80r:0) 0@48r  L000000000000000C [64r,80r:0) 0@64r  weight:0.000000e+00
%4 [80r,80d:0) 0@80r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function func: NoPHIs

0B      bb.0:
16B       INLINEASM &"" [attdialect], $0:[regdef:VGPR_32], def undef %1.sub0:vreg_64, $1:[regdef:VGPR_32], def undef %1.sub1:vreg_64
48B       undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
64B       %3.sub1:vreg_64 = COPY %3.sub0:vreg_64
72B       dead %2:vreg_64 = COPY %1:vreg_64
80B       dead %4:vreg_64 = COPY %3:vreg_64

After the second move, (main range got [16r,16d:1) in the constructMainRangeFromSubranges() before L000000000000000C was updated from [16r,72r:0) to [68r,72r:0))

%1 [16r,16d:1)[68r,72r:0) 0@68r 1@16r  L0000000000000003 [68r,72r:0) 0@68r  L000000000000000C [68r,72r:0) 0@68r  weight:0.000000e+00
%2 [72r,72d:0) 0@72r  weight:0.000000e+00
%3 [48r,64r:0)[64r,80r:1) 0@48r 1@64r  L0000000000000003 [48r,80r:0) 0@48r  L000000000000000C [64r,80r:0) 0@64r  weight:0.000000e+00
%4 [80r,80d:0) 0@80r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function func: NoPHIs

0B      bb.0:
48B       undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
64B       %3.sub1:vreg_64 = COPY %3.sub0:vreg_64
68B       INLINEASM &"" [attdialect], $0:[regdef:VGPR_32], def undef %1.sub0:vreg_64, $1:[regdef:VGPR_32], def undef %1.sub1:vreg_64
72B       dead %2:vreg_64 = COPY %1:vreg_64
80B       dead %4:vreg_64 = COPY %3:vreg_64

*** Bad machine code: No instruction at VNInfo def index ***
- function:    func
- basic block: %bb.0  (0x1bcd4b61968) [0B;96B)
- liverange:   [16r,16d:1)[68r,72r:0) 0@68r 1@16r
- v. register: %1
- ValNo:       1 (def 16r)

[rampitec]

LGTM, thanks! Please allow other reviewers time to review it too though.

llvm/lib/CodeGen/LiveIntervals.cpp

for (MachineOperand &MO : MI->operands()) {
         }
         updateRange(LI, Reg, LaneBitmask::getNone());
         // If main range has a hole and we are moving a subrange use across
         // the hole updateRange() cannot properly handle it since it only
         // gets the LiveRange and not the whole LiveInterval. As a result
         // we may end up with a main range not covering all subranges.
         // This is extremely rare case, so let's check and reconstruct the
         // main range.
+        if (LI.hasSubRanges()) {
+          unsigned SubReg = MO.getSubReg();
+          LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
+                                        : MRI.getMaxLaneMaskForVReg(Reg);
           for (LiveInterval::SubRange &S : LI.subranges()) {
-          if (LI.covers(S))
+            if ((S.LaneMask & LaneMask).none() || LI.covers(S))
               continue;
             LI.clear();
             LIS.constructMainRangeFromSubranges(LI);
             break;
           }
+        }
 
         continue;
       }
 
       // For physregs, only update the regunits that actually have a
       // precomputed live range.
       for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
            ++Units)

llvm/unittests/MI/LiveIntervalTest.cpp

 )MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
     MachineInstr &MI = getMI(MF, 3, /*BlockNum=*/1);
     MI.getOperand(0).setIsUndef(false);
     testHandleMove(MF, LIS, 4, 3, 1);
     testHandleMove(MF, LIS, 1, 4, 1);
   });
 }
 
+TEST(LiveIntervalTest, TestMoveSubRegsOfOneReg) {
+  liveIntervalTest(R"MIR(
+    INLINEASM &"", 0, 1835018, def undef %4.sub0:vreg_64, 1835018, def undef %4.sub1:vreg_64
+    %1:vreg_64 = COPY %4
+    undef %2.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+    %2.sub1:vreg_64 = COPY %2.sub0
+    %3:vreg_64 = COPY %2
+)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
+    testHandleMove(MF, LIS, 1, 4);
+    testHandleMove(MF, LIS, 0, 3);
+  });
+}
+
 TEST(LiveIntervalTest, BundleUse) {
   liveIntervalTest(R"MIR(
     %0 = IMPLICIT_DEF
     S_NOP 0
     S_NOP 0, implicit %0
     S_NOP 0
 )MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
     testHandleMoveIntoNewBundle(MF, LIS, 1, 2);