[PowerPC] PPCTLSDynamicCall does not preserve LiveIntervals

[foad]

Summary

According to D127731, PPCTLSDynamicCall does not preserve
LiveIntervals, so stop claiming that it does and remove the code
that tried to repair them. NFCI.

[nemanjai]

Is it possible to add a testcase that fails to verify or otherwise shows that a live range is computed incorrectly?

[foad]

Add a test and don't claim to preserve SlotIndexes either.

[nemanjai]

LGTM. Thanks for fixing this.

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

 namespace {
   struct PPCTLSDynamicCall : public MachineFunctionPass {
     static char ID;
     PPCTLSDynamicCall() : MachineFunctionPass(ID) {
       initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry());
     }
 
     const PPCInstrInfo *TII;
-    LiveIntervals *LIS;
 
 protected:
     bool processBlock(MachineBasicBlock &MBB) {
       bool Changed = false;
       bool NeedFence = true;
       bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
       bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI();
       bool IsPCREL = false;
bool processBlock(MachineBasicBlock &MBB) {
         }
 
         LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n    " << MI);
 
         Register OutReg = MI.getOperand(0).getReg();
         Register InReg = PPC::NoRegister;
         Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
         Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4;
-        SmallVector<Register, 3> OrigRegs = {OutReg, GPR3};
-        if (!IsPCREL) {
+        if (!IsPCREL)
           InReg = MI.getOperand(1).getReg();
-          OrigRegs.push_back(InReg);
-        }
         DebugLoc DL = MI.getDebugLoc();
 
         unsigned Opc1, Opc2;
         switch (MI.getOpcode()) {
         default:
           llvm_unreachable("Opcode inconsistency error");
         case PPC::ADDItlsgdLADDR:
           Opc1 = PPC::ADDItlsgdL;
bool processBlock(MachineBasicBlock &MBB) {
         // mflr in the prologue and the address in LR is clobbered (PR25839).
         // We don't really need to save data to the stack - the clobbered
         // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
         // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
         if (NeedFence)
           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
                                                               .addImm(0);
 
-        // The ADDItls* instruction is the first instruction in the
-        // repair range.
-        MachineBasicBlock::iterator First = I;
-        --First;
-
         if (IsAIX) {
           // The variable offset and region handle are copied in r4 and r3. The
           // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
           BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4)
               .addReg(MI.getOperand(1).getReg());
           BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
               .addReg(MI.getOperand(2).getReg());
           BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4);
bool processBlock(MachineBasicBlock &MBB) {
             Call->addOperand(MI.getOperand(3));
         }
         if (NeedFence)
           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
 
         BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
           .addReg(GPR3);
 
-        // The COPY is the last instruction in the repair range.
-        MachineBasicBlock::iterator Last = I;
-        --Last;
-
         // Move past the original instruction and remove it.
         ++I;
         MI.removeFromParent();
 
-        // Repair the live intervals.
-        LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
         Changed = true;
       }
 
       return Changed;
     }
 
 public:
   bool isPCREL(const MachineInstr &MI) {
     return (MI.getOpcode() == PPC::PADDI8pc) &&
            (MI.getOperand(2).getTargetFlags() ==
                 PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
             MI.getOperand(2).getTargetFlags() ==
                 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
   }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
-      LIS = &getAnalysis<LiveIntervals>();
 
       bool Changed = false;
 
       for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
         if (processBlock(B))
           Changed = true;
 
       return Changed;
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<LiveIntervals>();
-      AU.addPreserved<LiveIntervals>();
       AU.addRequired<SlotIndexes>();
-      AU.addPreserved<SlotIndexes>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
 }
 
 INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE,
                       "PowerPC TLS Dynamic Call Fixup", false, false)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
 INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE,
                     "PowerPC TLS Dynamic Call Fixup", false, false)
 
 char PPCTLSDynamicCall::ID = 0;
 FunctionPass*
 llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); }

llvm/test/CodeGen/PowerPC/tls-crash.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 -relocation-model=pic -run-pass=ppc-tls-dynamic-call,pipeliner -verify-machineinstrs %s -o - | FileCheck %s
+
+# Just check that MachineVerifier does not fail due to PPCTLSDynamicCall failing
+# to preserve some analyses.
+# CHECK: name: test
+
+--- |
+  %0 = type { i32 (...)**, %0* }
+  @x = external dso_local thread_local unnamed_addr global %0*, align 8
+  define void @test(i8* %arg) { ret void }
+...
+---
+name: test
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x3
+
+    %0:g8rc = COPY killed $x3
+    %1:g8rc_and_g8rc_nox0 = PADDI8pc 0, target-flags(ppc-pcrel, ppc-got, ppc-tlsld) @x
+    %2:g8rc_and_g8rc_nox0 = PADDIdtprel killed %1, target-flags(ppc-pcrel, ppc-got, ppc-tlsld) @x
+    STD killed %0, 0, killed %2 :: (store (s64) into `i8** bitcast (%0** @x to i8**)`)
+    BLR8 implicit $lr8, implicit $rm
+...