[AMDGPU] Limit GFX11 to using 128 VGPRs

[foad]

Summary

This is a temporary measure to avoid generating incorrect code until the
compiler understands the new way that GFX11 encodes 16-bit operands in
VOP instructions.

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 #define GET_INSTRMAP_INFO
 #include "AMDGPUGenInstrInfo.inc"
 
 static llvm::cl::opt<unsigned>
     AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden,
                             llvm::cl::desc("AMDHSA Code Object Version"),
                             llvm::cl::init(4));
 
+// TODO-GFX11: Remove this when full 16-bit codegen is implemented.
+static llvm::cl::opt<bool>
+    LimitTo128VGPRs("amdgpu-limit-to-128-vgprs", llvm::cl::Hidden,
+                    llvm::cl::desc("Never use more than 128 VGPRs"));
+
 namespace {
 
 /// \returns Bit mask for given bit \p Shift and bit \p Width.
 unsigned getBitMask(unsigned Shift, unsigned Width) {
   return ((1 << Width) - 1) << Shift;
 }
 
 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
   if (STI->getFeatureBits().test(FeatureGFX90AInsts))
     return 512;
   if (!isGFX10Plus(*STI))
     return 256;
   return STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1024 : 512;
 }
 
 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) {
+  if (LimitTo128VGPRs.getNumOccurrences() ? LimitTo128VGPRs
+                                          : isGFX11Plus(*STI)) {
+    // GFX11 changes the encoding of 16-bit operands in VOP1/2/C instructions
+    // such that values 128..255 no longer mean v128..v255, they mean
+    // v0.hi..v127.hi instead. Until the compiler understands this, it is not
+    // safe to use v128..v255.
+    // TODO-GFX11: Remove this when full 16-bit codegen is implemented.
+    return 128;
+  }
   if (STI->getFeatureBits().test(FeatureGFX90AInsts))
     return 512;
   return 256;
 }
 
 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
   assert(WavesPerEU != 0);
 

llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll

 ; GFX9: NumVgprs: 256
 ; GFX90A: NumVgprs: 256
 ; GFX90A: NumAgprs: 0
 ; GFX90A: TotalNumVgprs: 256
 ; GFX10WGP-WAVE32: NumVgprs: 256
 ; GFX10WGP-WAVE64: NumVgprs: 256
 ; GFX10CU-WAVE32: NumVgprs: 256
 ; GFX10CU-WAVE64: NumVgprs: 256
-; GFX11WGP-WAVE32: NumVgprs: 256
-; GFX11WGP-WAVE64: NumVgprs: 256
-; GFX11CU-WAVE32: NumVgprs: 256
-; GFX11CU-WAVE64: NumVgprs: 256
+; GFX11WGP-WAVE32: NumVgprs: 128
+; GFX11WGP-WAVE64: NumVgprs: 128
+; GFX11CU-WAVE32: NumVgprs: 128
+; GFX11CU-WAVE64: NumVgprs: 128
 define amdgpu_kernel void @f256() #256 {
   call void @use256vgprs()
   ret void
 }
 attributes #256 = { nounwind "amdgpu-flat-work-group-size"="256,256" }
 
 ; GCN-LABEL: {{^}}f512:
 ; GFX9: NumVgprs: 128
 ; GFX90A: NumVgprs: 128
 ; GFX90A: NumAgprs: 128
 ; GFX90A: TotalNumVgprs: 256
 ; GFX10WGP-WAVE32: NumVgprs: 256
 ; GFX10WGP-WAVE64: NumVgprs: 256
 ; GFX10CU-WAVE32: NumVgprs: 128
 ; GFX10CU-WAVE64: NumVgprs: 128
-; GFX11WGP-WAVE32: NumVgprs: 256
-; GFX11WGP-WAVE64: NumVgprs: 256
+; GFX11WGP-WAVE32: NumVgprs: 128
+; GFX11WGP-WAVE64: NumVgprs: 128
 ; GFX11CU-WAVE32: NumVgprs: 128
 ; GFX11CU-WAVE64: NumVgprs: 128
 define amdgpu_kernel void @f512() #512 {
   call void @foo()
   call void @use256vgprs()
   ret void
 }
 attributes #512 = { nounwind "amdgpu-flat-work-group-size"="512,512" }