Don't use the S30 and S31 regs for the pic code .

[umesh.kalappa0]

Summary

These changes to address the https://github.com/llvm/llvm-project/issues/55857 issue .

Solution proposed was , Since R30/S30 used as pointer (32 bits ) for GOT Table in the ppc32 ABI ,so remove from the SPE callee save register when pic enabled .

So you don't emit the spe load and store inst for S30 and S31 regs.

[chmeee]

llvm/lib/Target/PowerPC/PPCCallingConv.td

280

Should we also drop S31? R31 is the frame pointer typically, so should almost never be an SPE register in the ABI.

[umesh.kalappa0]

llvm/lib/Target/PowerPC/PPCCallingConv.td

280

Agree and updated the changes.

[chmeee]

I'm not sure of the proper use of S31 in general, since ABI makes r31 the frame pointer in general. If we stick with only supporting the ABI, and not supporting alternatives, I think S31 should just be removed in general, unless we support omitting the frame pointer.

But I think in general S31 shouldn't be conditional on PIC, since its use is orthogonal. Maybe a different change?

llvm/lib/Target/PowerPC/PPCCallingConv.td

275

Should S31 be dropped up here, too? Or should this remain as the list of all callee saved registers?

[umesh.kalappa0]

llvm/lib/Target/PowerPC/PPCCallingConv.td

275

Taken care

[umesh.kalappa0]

@chmee and @nemanjai . ,Please do you have any other comments or ok to commit the same ?

[umesh.kalappa0]

@chmeee ,Can you commit for us ,since we don't have the commit access for the repo.

[chmeee]

In D127495#3581809, @umesh.kalappa0 wrote:

@chmeee ,Can you commit for us ,since we don't have the commit access for the repo.

Sorry, but my computer with the relevant keys is in storage for a pending move, so I won't be able to commit for a month or so. @nemanjai is better positioned to do it.

[umesh.kalappa0]

In D127495#3582591, @chmeee wrote:

In D127495#3581809, @umesh.kalappa0 wrote:

@chmeee ,Can you commit for us ,since we don't have the commit access for the repo.

Sorry, but my computer with the relevant keys is in storage for a pending move, so I won't be able to commit for a month or so. @nemanjai is better positioned to do it.

@nemanjai ,Please do needful.

[umesh.kalappa0]

fixed the testcase to adhere changes.

[nemanjai]

Sorry about the delay in committing this.

llvm/lib/Target/PowerPC/PPCCallingConv.td

def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
                                           R21, R22, R23, R24, R25, R26, R27,
                                           R28, R29, R30, R31, CR2, CR3, CR4
                                       )>;
 def CSR_SVR432 :  CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31
                                    )>;
 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
-                                   S23, S24, S25, S26, S27, S28, S29, S30, S31
-                              )>;
+                                   S23, S24, S25, S26, S27, S28, S29, S30 
+                              )>;
+
+def CSR_SPE_NO_S30_31 : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21,
+                  S22, S23, S24, S25, S26, S27, S28, S29
+            )>;
 
 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 
 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
 
+def CSR_SVR432_SPE_NO_S30_31 : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE_NO_S30_31)>;
+
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,
                                      F19, F20, F21, F22, F23, F24, F25, F26,
                                      F27, F28, F29, F30, F31, CR2, CR3, CR4
                                 )>;
 
 def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (Subtarget.hasAltivec())
       return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
                                            : CSR_AIX32_SaveList;
     return CSR_AIX32_SaveList;
   }
   if (Subtarget.pairedVectorMemops())
     return CSR_SVR432_VSRP_SaveList;
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
-  else if (Subtarget.hasSPE())
+  else if (Subtarget.hasSPE()) {
+    if (TM.isPositionIndependent() && !TM.isPPC64())
+      return CSR_SVR432_SPE_NO_S30_31_SaveList;
     return CSR_SVR432_SPE_SaveList;
+   }
   return CSR_SVR432_SaveList;
 }
 
 const uint32_t *
 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                       CallingConv::ID CC) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
return Subtarget.pairedVectorMemops()
                ? CSR_SVR464_VSRP_RegMask
                : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
                                          : CSR_PPC64_RegMask);
   else
     return Subtarget.pairedVectorMemops()
                ? CSR_SVR432_VSRP_RegMask
                : (Subtarget.hasAltivec()
                       ? CSR_SVR432_Altivec_RegMask
-                      : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
-                                            : CSR_SVR432_RegMask));
+                      : (Subtarget.hasSPE()
+                             ? (TM.isPositionIndependent()
+                                     ? CSR_SVR432_SPE_NO_S30_31_RegMask
+                                     : CSR_SVR432_SPE_RegMask)
 }
 
 const uint32_t*
 PPCRegisterInfo::getNoPreservedMask() const {
   return CSR_NoRegs_RegMask;
 }
 
 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {

llvm/test/CodeGen/PowerPC/pr55857.ll

+; RUN: llc --relocation-model=pic  \
+; RUN:   -mtriple=ppc32 < %s | FileCheck  %s 
+
+@g = global i32 10, align 4
+
+; Function Attrs: noinline nounwind optnone uwtable
+define i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK-NOT: evstdd
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, ptr %retval, align 4
+  %0 = load i32, ptr @g, align 4
+  ret i32 %0
+}
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="e500" "target-features"="+spe,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-vsx" }
+

llvm/test/CodeGen/PowerPC/spe.ll

 
 declare void @test_memset(i8* nocapture writeonly, i8, i32, i1)
 @global_var1 = global i32 0, align 4
 define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) #0 {
 ; SPE-LABEL: test_spill:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr 0
 ; SPE-NEXT:    stw 0, 4(1)
-; SPE-NEXT:    stwu 1, -272(1)
+; SPE-NEXT:    stwu 1, -288(1)
 ; SPE-NEXT:    li 5, 256
-; SPE-NEXT:    evstddx 30, 1, 5 # 8-byte Folded Spill
-; SPE-NEXT:    li 5, 264
-; SPE-NEXT:    evstddx 31, 1, 5 # 8-byte Folded Spill
-; SPE-NEXT:    li 5, .LCPI55_0@l
+; SPE-NEXT:    evstddx 30, 1, 5  # 8-byte Folded Spill
+; SPE-NEXT:    li 5, .LCPI55_0@
 ; SPE-NEXT:    lis 6, .LCPI55_0@ha
 ; SPE-NEXT:    evlddx 5, 6, 5
+; SPE-NEXT:    stw 31, 284(1)    # 4-byte Folded Spill
 ; SPE-NEXT:    evstdd 14, 128(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 15, 136(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 16, 144(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 17, 152(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 18, 160(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 19, 168(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 20, 176(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 21, 184(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 22, 192(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 23, 200(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 24, 208(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 25, 216(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 26, 224(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 27, 232(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 28, 240(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 29, 248(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evmergelo 3, 3, 4
-; SPE-NEXT:    lwz 4, 280(1)
+; SPE-NEXT:    lwz 4, 296(1)
 ; SPE-NEXT:    efdadd 3, 3, 3
 ; SPE-NEXT:    efdadd 3, 3, 5
 ; SPE-NEXT:    evstdd 3, 24(1) # 8-byte Folded Spill
 ; SPE-NEXT:    stw 4, 20(1) # 4-byte Folded Spill
 ; SPE-NEXT:    #APP
 ; SPE-NEXT:    #NO_APP
 ; SPE-NEXT:    addi 3, 1, 76
 ; SPE-NEXT:    li 4, 0
 ; SPE-NEXT:    li 5, 24
 ; SPE-NEXT:    li 6, 1
 ; SPE-NEXT:    li 30, 0
 ; SPE-NEXT:    bl test_memset
 ; SPE-NEXT:    lwz 3, 20(1) # 4-byte Folded Reload
 ; SPE-NEXT:    stw 30, 0(3)
 ; SPE-NEXT:    bl test_func2
 ; SPE-NEXT:    addi 3, 1, 32
 ; SPE-NEXT:    li 4, 0
 ; SPE-NEXT:    li 5, 20
 ; SPE-NEXT:    li 6, 1
 ; SPE-NEXT:    bl test_memset
 ; SPE-NEXT:    evldd 4, 24(1) # 8-byte Folded Reload
-; SPE-NEXT:    li 5, 264
-; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    evlddx 31, 1, 5 # 8-byte Folded Reload
 ; SPE-NEXT:    li 5, 256
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; SPE-NEXT:    evmergehi 3, 4, 4
 ; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    evlddx 30, 1, 5 # 8-byte Folded Reload
+; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    evldd 29, 248(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 28, 240(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 27, 232(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 26, 224(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 25, 216(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 24, 208(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 23, 200(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 22, 192(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 21, 184(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 20, 176(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 19, 168(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 18, 160(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 17, 152(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 16, 144(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 15, 136(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 14, 128(1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz 0, 276(1)
-; SPE-NEXT:    addi 1, 1, 272
+; SPE-NEXT:    lwz 31, 284(1)   # 4-byte Folded Reload
+; SPE-NEXT:    lwz 0, 292(1)
+; SPE-NEXT:    addi 1, 1, 288
 ; SPE-NEXT:    mtlr 0
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_spill:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -144(1)