llvm-reduce: Don't set generic instruction operands to undef

[arsenm]

Summary

The intention is that these should never have undef operands. It turns
out the restriction the verifier enforces is too lax. The verifier
enforces that registers without a register class cannot be undef, but
it's valid to use a register with a register class and type. The
verifier needs to change to be based on the opcode.

[paquette]

I think this seems reasonable, but if this is a problem with the verifier, why not fix it there? Or would that not work?

[arsenm]

In D127112#3560654, @paquette wrote:

I think this seems reasonable, but if this is a problem with the verifier, why not fix it there? Or would that not work?

The verifier problem is separate. The verifier is too lenient. This is following the stricter standard the verifier should enforce

[paquette]

Ok, LGTM then

[arsenm]

cbbc7e4a7572db4a3ddc008a64f22893220296ef

llvm/test/tools/llvm-reduce/mir/generic-vreg.mir

 # REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -abort-on-invalid-reduction -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # Verify that reduction works with generic virtual registers, and the
 # properties like register banks, types and names.
 
 
 # CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
 # CHECK-INTERESTINGNESS: G_BITCAST

llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir

+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# Generic instructions should not have undef set on operands
+# CHECK-INTERESTINGNESS: G_ADD
+
+# RESULT: %1:vreg_64(s64) = IMPLICIT_DEF
+# RESULT: %add:_(s64) = G_ADD %1, %1
+
+---
+name: func
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
+
+    %0:vgpr(s32) = G_IMPLICIT_DEF
+    %1:vreg_64(s64) = IMPLICIT_DEF
+    %add:_(s64) = G_ADD %1, %1
+    %ptr:_(p1) = G_IMPLICIT_DEF
+    G_STORE %0(s32), %ptr(p1) :: (store (s32), addrspace 1)
+    S_ENDPGM 0, implicit %add(s64), implicit %1(s64)
+
+...

llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp

 
 using namespace llvm;
 
 static void removeUsesFromFunction(Oracle &O, MachineFunction &MF) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {
+      // Generic instructions are not supposed to have undef operands.
+      if (isPreISelGenericOpcode(MI.getOpcode()))
+        continue;
+
       int NumOperands = MI.getNumOperands();
       int NumRequiredOps = MI.getNumExplicitOperands() +
                            MI.getDesc().getNumImplicitDefs() +
                            MI.getDesc().getNumImplicitUses();
 
       for (int I = NumOperands - 1; I >= 0; --I) {
         MachineOperand &MO = MI.getOperand(I);
         if (!MO.isReg() || !MO.readsReg())