[ARM] Make narrow push/pop in SEH prologues/epilogues where applicable

[mstorsjo]

Summary

We intentionally disable Thumb2SizeReduction for SEH
prologues/epilogues, to avoid needing to guess what will happen with
the instructions in a potential future pass in frame lowering.

But for this specific case, where we know we can express the
intent with a narrow instruction, change to that instruction form
directly in frame lowering.

I'm unsure if there's some other set of MachineInstr properties I should
copy over here - I didn't try to follow all the generic bits of
Thumb2SizeReduction - this at least seems to work for my testcases;
it only needs to work for these three specific instructions.

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMFrameLowering.cpp

MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
               .addImm(/*Wide=*/1)
               .setMIFlags(Flags);
     break;
 
   case ARM::t2LDMIA_RET:
   case ARM::t2LDMIA_UPD:
   case ARM::t2STMDB_UPD: {
     unsigned Mask = 0;
+    bool Wide = false;
     for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
       const MachineOperand &MO = MBBI->getOperand(i);
       if (!MO.isReg() || MO.isImplicit())
         continue;
       unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());
       if (Reg == 15)
         Reg = 14;
+      if (Reg >= 8 && Reg <= 13)
+        Wide = true;
+      else if (Opc == ARM::t2LDMIA_UPD && Reg == 14)
+        Wide = true;
       Mask |= 1 << Reg;
     }
+    if (!Wide) {
+      unsigned NewOpc;
+      switch (Opc) {
+      case ARM::t2LDMIA_RET:
+        NewOpc = ARM::tPOP_RET;
+        break;
+      case ARM::t2LDMIA_UPD:
+        NewOpc = ARM::tPOP;
+        break;
+      case ARM::t2STMDB_UPD:
+        NewOpc = ARM::tPUSH;
+        break;
+      default:
+        llvm_unreachable("");
+      }
+      MachineInstrBuilder NewInstr =
+          BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags());
+      for (unsigned i = 2, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)
+        NewInstr.add(MBBI->getOperand(i));
+      MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);
+      MBB->erase(MBBI);
+      MBBI = NewMBBI;
+    }
     unsigned SEHOpc =
         (Opc == ARM::t2LDMIA_RET) ? ARM::SEH_SaveRegs_Ret : ARM::SEH_SaveRegs;
     MIB = BuildMI(MF, DL, TII.get(SEHOpc))
               .addImm(Mask)
-              .addImm(/*Wide=*/1)
+              .addImm(Wide ? 1 : 0)
               .setMIFlags(Flags);
     break;
   }
   case ARM::VSTMDDB_UPD:
   case ARM::VLDMDIA_UPD: {
     int First = -1, Last = 0;
     for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
       const MachineOperand &MO = MBBI->getOperand(i);

llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll

entry:
   call arm_aapcs_vfpcc void @other()
   call void asm sideeffect "", "~{r4}"()
   ret void
 }
 
 ; CHECK-LABEL: clobberR4NoFrame:
 ; CHECK-NEXT: .seh_proc clobberR4NoFrame
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
-; CHECK-NEXT:         push.w  {r4, lr}
-; CHECK-NEXT:         .seh_save_regs_w  {r4, lr}
+; CHECK-NEXT:         push    {r4, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4, lr}
 ; CHECK-NEXT:         .seh_endprologue
 ; CHECK-NEXT:         bl      other
 
 ; CHECK:              .seh_startepilogue
-; CHECK-NEXT:         pop.w   {r4, pc}
-; CHECK-NEXT:         .seh_save_regs_w  {r4, lr}
+; CHECK-NEXT:         pop     {r4, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4, lr}
 ; CHECK-NEXT:         .seh_endepilogue
 ; CHECK-NEXT:         .seh_endproc
 
 define arm_aapcs_vfpcc void @clobberR4NoFrame() uwtable "frame-pointer"="none" {
 entry:
   call arm_aapcs_vfpcc void @other()
   call void asm sideeffect "", "~{r4}"()
   ret void
 }
 
 ; CHECK-LABEL: clobberR4Tail:
 ; CHECK-NEXT: .seh_proc clobberR4Tail
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
-; CHECK-NEXT:         push.w  {r4, lr}
-; CHECK-NEXT:         .seh_save_regs_w  {r4, lr}
+; CHECK-NEXT:         push    {r4, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4, lr}
 ; CHECK-NEXT:         .seh_endprologue
 
 ; CHECK:              .seh_startepilogue
 ; CHECK-NEXT:         pop.w   {r4, lr}
 ; CHECK-NEXT:         .seh_save_regs_w        {r4, lr}
 ; CHECK-NEXT:         b.w     other
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         .seh_endepilogue
entry:
   call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
   call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %buf)
   ret void
 }
 
 ; CHECK-LABEL: func5000:
 ; CHECK-NEXT: .seh_proc func5000
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
-; CHECK-NEXT:         push.w  {r4, r5, r6, lr}
-; CHECK-NEXT:         .seh_save_regs_w  {r4-r6, lr}
+; CHECK-NEXT:         push    {r4, r5, r6, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
 ; CHECK-NEXT:         movw    r4, #1250
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         bl      __chkstk
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         sub.w   sp, sp, r4
 ; CHECK-NEXT:         .seh_stackalloc_w       5000
 ; CHECK-NEXT:         .seh_endprologue
 
 ; CHECK:              .seh_startepilogue
 ; CHECK-NEXT:         add.w   sp, sp, #4992
 ; CHECK-NEXT:         .seh_stackalloc_w       4992
 ; CHECK-NEXT:         add     sp, #8
 ; CHECK-NEXT:         .seh_stackalloc 8
-; CHECK-NEXT:         pop.w   {r4, r5, r6, pc}
-; CHECK-NEXT:         .seh_save_regs_w  {r4-r6, lr}
+; CHECK-NEXT:         pop     {r4, r5, r6, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
 ; CHECK-NEXT:         .seh_endepilogue
 ; CHECK-NEXT:         .seh_endproc
 
 define arm_aapcs_vfpcc void @func5000() {
 entry:
   %buf = alloca [5000 x i8], align 1
   call void @llvm.lifetime.start.p0(i64 5000, ptr nonnull %buf)
   call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
   call void @llvm.lifetime.end.p0(i64 5000, ptr nonnull %buf)
   ret void
 }
 
 ; CHECK-LABEL: func262144:
 ; CHECK-NEXT: .seh_proc func262144
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
-; CHECK-NEXT:         push.w  {r4, r5, r6, lr}
-; CHECK-NEXT:         .seh_save_regs_w  {r4-r6, lr}
+; CHECK-NEXT:         push    {r4, r5, r6, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
 ; CHECK-NEXT:         movw    r4, #0
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         movt    r4, #1
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         bl      __chkstk
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         sub.w   sp, sp, r4
 ; CHECK-NEXT:         .seh_stackalloc_w       262144
 ; CHECK-NEXT:         .seh_endprologue
 
 ; CHECK:              .seh_startepilogue
 ; CHECK-NEXT:         add.w   sp, sp, #262144
 ; CHECK-NEXT:         .seh_stackalloc_w       262144
-; CHECK-NEXT:         pop.w   {r4, r5, r6, pc}
-; CHECK-NEXT:         .seh_save_regs_w  {r4-r6, lr}
+; CHECK-NEXT:         pop     {r4, r5, r6, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
 ; CHECK-NEXT:         .seh_endepilogue
 ; CHECK-NEXT:         .seh_endproc
 
 define arm_aapcs_vfpcc void @func262144() {
 entry:
   %buf = alloca [262144 x i8], align 1
   call void @llvm.lifetime.start.p0(i64 262144, ptr nonnull %buf)
   call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
   call void @llvm.lifetime.end.p0(i64 262144, ptr nonnull %buf)
   ret void
 }
 
 ; CHECK-LABEL: func270000:
 ; CHECK-NEXT: .seh_proc func270000
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
-; CHECK-NEXT:         push.w  {r4, r5, r6, lr}
-; CHECK-NEXT:         .seh_save_regs_w  {r4-r6, lr}
+; CHECK-NEXT:         push    {r4, r5, r6, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
 ; CHECK-NEXT:         movw    r4, #1964
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         movt    r4, #1
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         bl      __chkstk
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         sub.w   sp, sp, r4
 ; CHECK-NEXT:         .seh_stackalloc_w       270000
 ; CHECK-NEXT:         .seh_endprologue
 
 ; CHECK:              .seh_startepilogue
 ; CHECK-NEXT:         add.w   sp, sp, #268288
 ; CHECK-NEXT:         .seh_stackalloc_w       268288
 ; CHECK-NEXT:         add.w   sp, sp, #1712
 ; CHECK-NEXT:         .seh_stackalloc_w       1712
-; CHECK-NEXT:         pop.w   {r4, r5, r6, pc}
-; CHECK-NEXT:         .seh_save_regs_w  {r4-r6, lr}
+; CHECK-NEXT:         pop     {r4, r5, r6, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
 ; CHECK-NEXT:         .seh_endepilogue
 ; CHECK-NEXT:         .seh_endproc
 
 define arm_aapcs_vfpcc void @func270000() {
 entry:
   %buf = alloca [270000 x i8], align 1
   call void @llvm.lifetime.start.p0(i64 270000, ptr nonnull %buf)
   call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
   call void @llvm.lifetime.end.p0(i64 270000, ptr nonnull %buf)
   ret void
 }
 
 declare arm_aapcs_vfpcc void @useptr(ptr noundef)

llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll

 ; OBJ-NEXT: }
 ; OBJ-NEXT: DefRangeRegisterRelSym {
 ; OBJ-NEXT:   Kind: S_DEFRANGE_REGISTER_REL (0x1145)
 ; OBJ-NEXT:   BaseRegister: ARM_SP (0x17)
 ; OBJ-NEXT:   HasSpilledUDTMember: No
 ; OBJ-NEXT:   OffsetInParent: 0
 ; OBJ-NEXT:   BasePointerOffset: 12
 ; OBJ-NEXT:   LocalVariableAddrRange {
-; OBJ-NEXT:     OffsetStart: .text+0xA
+; OBJ-NEXT:     OffsetStart: .text+0x8
 ; OBJ-NEXT:     ISectStart: 0x0
-; OBJ-NEXT:     Range: 0x1C
+; OBJ-NEXT:     Range: 0x1A
 ; OBJ-NEXT:   }
 ; OBJ-NEXT: }
 
 ; ModuleID = 'test.c'
 source_filename = "test.c"
 target datalayout = "e-m:w-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "thumbv7-pc-windows-msvc19.11.0"