[AMDGPU][MC][GFX11] Support base+soffset+offset SMEM loads.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

142

Looks like we have a use case for classes in multiclasses?

[dp]

llvm/lib/Target/AMDGPU/SMInstructions.td

1143

Is the _COMMON variant defined for aesthetic reasons? I believe the following code should work:

def : MnemonicAlias<!cast<SM_Load_Pseudo>(ps#"_IMM").Mnemonic, opName>,

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

1143

The aim here is to make the code reflect the fact that the pseudos share the same mnemonic (and I'm not sure casting to SM_Load_Pseudo instead of SM_Pseudo makes it obvious enough). This introduces a pseudo that is not used as such, but that seems a result of using pseudos to describe instruction properties -- a problem that we might want to address separately at some point.

[dp]

llvm/lib/Target/AMDGPU/SMInstructions.td

1143

This is a matter of taste, but for me the _COMMON definition does not make code clearer because the purpose of this definition is not immediately obvious. Maybe the name is a bit misleading and something like _MNEMO would be better?

Another (more important) problem is that the _COMMON definition if not for free - it contaminates compiler tables with unused entries.

[kosarev]

Removed the _COMMON pseudos.

[dp]

LGTM.

llvm/lib/Target/AMDGPU/SMInstructions.td

class SM_Discard_Pseudo <string opName, dag ins, bit isImm>
   let has_offset = isImm;
   let has_soffset = !not(isImm);
   let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
 }
 
 multiclass SM_Pseudo_Loads<string opName,
                            RegisterClass baseClass,
                            RegisterClass dstClass> {
   def _IMM  : SM_Load_Pseudo <opName,
                               (outs dstClass:$sdst),
                               (ins baseClass:$sbase, i32imm:$offset, CPol:$cpol),
                               " $sdst, $sbase, $offset$cpol", []> {
     let has_offset = 1;
     let BaseClass = baseClass;
     let PseudoInstr = opName # "_IMM";
     let has_glc = 1;
     let has_dlc = 1;
class SMEM_Real_gfx11<bits<8> op, SM_Pseudo ps, string opName = ps.Mnemonic> :
   let Inst{13}    = !if(ps.has_dlc, cpol{CPolBit.DLC}, 0);
   let Inst{14}    = !if(ps.has_glc, cpol{CPolBit.GLC}, 0);
   // There are SMEM instructions that do not employ any of the offset
   // fields, in which case we need them to remain undefined.
   let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
                         !if(ps.has_offset, !cast<int>(SGPR_NULL_gfx11plus.HWEncoding), ?));
 }
 
-multiclass SM_Real_Loads_gfx11<bits<8> op, string ps, string opName,
-                               SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
-                               SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
-  def _IMM_gfx11 : SMEM_Real_gfx11<op, immPs, opName> {
-    let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
-  }
-  def _SGPR_gfx11 : SMEM_Real_gfx11<op, sgprPs, opName> {
-    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
-  }
-  def : MnemonicAlias<immPs.Mnemonic, opName>, Requires<[isGFX11Plus]>;
+class SMEM_Real_Load_gfx11<bits<8> op, string ps, string opName, dag offsets> :
+    SMEM_Real_gfx11<op, !cast<SM_Pseudo>(ps), opName> {
+  RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps).BaseClass;
+  let InOperandList = !con((ins BaseClass:$sbase), offsets, (ins CPol:$cpol));
+
+multiclass SM_Real_Loads_gfx11<bits<8> op, string ps, string opName> {
+  def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_IMM", opName, (ins smem_offset:$offset)>;
+  def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR", opName, (ins SReg_32:$soffset)>;
+  def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<
+    op, ps#"_SGPR_IMM", opName, (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
+  def : MnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName>,
+                      Requires<[isGFX11Plus]>;
 }
 
 defm S_LOAD_B32  : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD", "s_load_b32">;
 defm S_LOAD_B64  : SM_Real_Loads_gfx11<0x001, "S_LOAD_DWORDX2", "s_load_b64">;
 defm S_LOAD_B128 : SM_Real_Loads_gfx11<0x002, "S_LOAD_DWORDX4", "s_load_b128">;
 defm S_LOAD_B256 : SM_Real_Loads_gfx11<0x003, "S_LOAD_DWORDX8", "s_load_b256">;
 defm S_LOAD_B512 : SM_Real_Loads_gfx11<0x004, "S_LOAD_DWORDX16", "s_load_b512">;
 

llvm/test/MC/AMDGPU/gfx11_asm_smem.s

 // GFX11: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd6]
 
 s_load_b32 s5, s[2:3], m0
 // GFX11: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
 
 s_load_b32 s5, s[2:3], 0x0
 // GFX11: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
 
+s_load_b32 s5, s[2:3], s7 offset:0x12345
+// GFX11: encoding: [0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x0e]
+
 s_load_b32 s5, s[2:3], s0 glc
 // GFX11: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_b32 s5, s[2:3], s0 dlc
 // GFX11: encoding: [0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_b32 s5, s[2:3], s0 glc dlc
 // GFX11: encoding: [0x41,0x61,0x00,0xf4,0x00,0x00,0x00,0x00]

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt

 0x72,0x01,0x00,0xf4,0x00,0x00,0x00,0x00
 
 # GFX11: s_load_b32 s5, s[2:3], null             ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
 0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX11: s_load_b32 s5, s[2:3], 0x1234 glc dlc   ; encoding: [0x41,0x61,0x00,0xf4,0x34,0x12,0x00,0xf8]
 0x41,0x61,0x00,0xf4,0x34,0x12,0x00,0xf8
 
+# GFX11: s_load_b32 s5, s[2:3], s7 offset:0x12345 ; encoding: [0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x0e]
+0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x0e
+
 # GFX11: s_load_b32 s5, s[2:3], m0               ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
 0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX11: s_load_b32 s5, s[2:3], s0               ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0x00
 
 # GFX11: s_load_b32 s5, s[2:3], s0 dlc           ; encoding: [0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00