[PowerPC] use BL without nop for some internal calls for fast-isel.

[shchenz]

Summary

This fixes pr55607. Now we can generate BL without nop instruction for internal function for fast-isel.

[nemanjai]

The more analysis we do in FastISel, the less "fast" it becomes. And the tradeoff here is simply a nop after a call which hardly seems like a concern at -O0.

[shchenz]

In D126205#3535827, @nemanjai wrote:

The more analysis we do in FastISel, the less "fast" it becomes. And the tradeoff here is simply a nop after a call which hardly seems like a concern at -O0.

I am fine to abandon this.

But see the touched lines FIXME: We can and should optimize away the NOP for local calls.. And I tested other compilers like xlc/gcc on PowerPC, they are both not generating nop for O0. The nop may also have impact to the linker?

@umesh.kalappa0 are you OK we abandon this patch and cancel the PR https://github.com/llvm/llvm-project/issues/55607?

[shchenz]

As discussed, use option to disable fast-isel to avoid the redundant nop for issue https://github.com/llvm/llvm-project/issues/55607.

llvm/lib/Target/PowerPC/PPCFastISel.cpp

if (!GV) {
     // here (that will be generated, as necessary, during asm printing), and
     // the call we generate here will be erased by FastISel::selectPatchpoint,
     // so don't try very hard...
     if (CLI.IsPatchPoint)
       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
     else
       return false;
   } else {
-    // Build direct call with NOP for TOC restore.
-    // FIXME: We can and should optimize away the NOP for local calls.
-    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-                  TII.get(PPC::BL8_NOP));
+    // Build direct call.
+    bool ShareTOCBase = !Subtarget->isUsingPCRelativeCalls() &&
+                        Subtarget->getTargetLowering()->callsShareTOCBase(
+                            &FuncInfo.MF->getFunction(), GV);
+    unsigned CallOP = ShareTOCBase ? PPC::BL8 : PPC::BL8_NOP;
+    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOP));
     // Add callee.
     MIB.addGlobalAddress(GV);
   }
 
   // Add implicit physical register uses to the call.
   for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
     MIB.addReg(RegArgs[II], RegState::Implicit);
 

llvm/test/CodeGen/PowerPC/pr55607.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -fast-isel \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+define dso_local signext i32 @callee() {
+; CHECK-LABEL: callee:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i32 0
+}
+
+define dso_local signext i32 @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -112(r1)
+; CHECK-NEXT:    bl callee
+; CHECK-NEXT:    mr r30, r3
+; CHECK-NEXT:    bl callee2
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    add r3, r30, r3
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    addi r1, r1, 112
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+entry:
+  %call = call signext i32 @callee()
+  %call1 = call signext i32 @callee2()
+  %add = add nsw i32 %call, %call1
+  ret i32 %add
+}
+
+declare signext i32 @callee2()