[SystemZ] Bugfix for symbolic displacments.

[jonpa]

Summary

Properly handle the case where only the second operand of e.g. an MVC instruction uses a fixup for the displacement.

ouch... This was my bad - going back to your original idea from Nov 12 last year (https://reviews.llvm.org/D113341).

[uweigand]

LGTM, thanks!

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

 #define DEBUG_TYPE "mccodeemitter"
 
 namespace {
 
 class SystemZMCCodeEmitter : public MCCodeEmitter {
   const MCInstrInfo &MCII;
   MCContext &Ctx;
 
+  mutable unsigned MemOpsEmitted;
+
 public:
   SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
     : MCII(mcii), Ctx(ctx) {
   }
 
   ~SystemZMCCodeEmitter() override = default;
 
   // OVerride MCCodeEmitter.

 
 void SystemZMCCodeEmitter::
 encodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const {
   verifyInstructionPredicates(MI,
                               computeAvailableFeatures(STI.getFeatureBits()));
 
+  MemOpsEmitted = 0;
   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
   unsigned Size = MCII.get(MI.getOpcode()).getSize();
   // Big-endian insertion of Size bytes.
   unsigned ShiftValue = (Size * 8) - 8;
   for (unsigned I = 0; I != Size; ++I) {
     OS << uint8_t(Bits >> ShiftValue);
     ShiftValue -= 8;
   }
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
   llvm_unreachable("Unexpected operand type!");
 }
 
 uint64_t SystemZMCCodeEmitter::
 getDispOpValue(const MCInst &MI, unsigned OpNum,
                SmallVectorImpl<MCFixup> &Fixups,
                SystemZ::FixupKind Kind) const {
   const MCOperand &MO = MI.getOperand(OpNum);
-  if (MO.isImm())
+  if (MO.isImm()) {
+    ++MemOpsEmitted;
     return static_cast<uint64_t>(MO.getImm());
+  }
   if (MO.isExpr()) {
     // All instructions follow the pattern where the first displacement has a
     // 2 bytes offset, and the second one 4 bytes.
-    unsigned ByteOffs = Fixups.size() == 0 ? 2 : 4;
+    unsigned ByteOffs = MemOpsEmitted++ == 0 ? 2 : 4;
     Fixups.push_back(MCFixup::create(ByteOffs, MO.getExpr(), (MCFixupKind)Kind,
                                      MI.getLoc()));
     assert(Fixups.size() <= 2 && "More than two memory operands in MI?");
     return 0;
   }
   llvm_unreachable("Unexpected operand type!");
 }
 

llvm/test/MC/SystemZ/fixups.s

 
 ##BDV12
 # CHECK: vgeg %v0, src(%v0,%r1), 0              # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x12]
 # CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         vgeg %v0, src(%v0,%r1), 0
 
+## Fixup for second operand only
+# CHECK:  mvc     32(8,%r0), src                # encoding: [0xd2,0x07,0x00,0x20,0b0000AAAA,A]
+# CHECK-NEXT:                                   # fixup A - offset: 4, value: src, kind: FK_390_12
+        .align 16
+        mvc     32(8,%r0),src
 
 # Data relocs
 # llvm-mc does not show any "encoding" string for data, so we just check the relocs
 
 # CHECK-REL: .rela.data
   .data
 
 # CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LE64 target 0x0