[AMDGPU][MC][GFX7] Disable cache policy modifiers with SMEM

[foad]

Title should be "Disable ..." not "Disabled ...".

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
   int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
                                            AMDGPU::OpName::cpol);
   if (CPolPos == -1)
     return true;
 
   unsigned CPol = Inst.getOperand(CPolPos).getImm();
 
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
-  if ((TSFlags & (SIInstrFlags::SMRD)) &&
-      (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) {
-    Error(IDLoc, "invalid cache policy for SMRD instruction");
+  if (TSFlags & SIInstrFlags::SMRD) {
+    if (CPol && (isSI() || isCI())) {
+      SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
+      Error(S, "cache policy is not supported for SMRD instructions");
+      return false;
+    }
+    if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) {
+      Error(IDLoc, "invalid cache policy for SMEM instruction");
       return false;
     }
+  }
 
   if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
     SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
     StringRef CStr(S.getPointer());
     S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);
     Error(S, "scc is not supported on this GPU");
     return false;
   }

llvm/lib/Target/AMDGPU/SMInstructions.td

class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
   let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
   let Inst{8}     = ps.has_offset;
   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
   let Inst{26-22} = op;
   let Inst{31-27} = 0x18; //encoding
 }
 
-// FIXME: Assembler should reject trying to use glc on SMRD
-// instructions on SI.
 multiclass SM_Real_Loads_si<bits<5> op, string ps,
                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
 
   def _IMM_si : SMRD_Real_si <op, immPs> {
     let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, CPol:$cpol);
   }
 

llvm/test/MC/AMDGPU/cpol-err.s

 // CHECK-NEXT:{{^}}                                            ^
 
 global_atomic_add v[3:4], v5, off slc noglc glc
 // CHECK: error: duplicate cache policy modifier
 // CHECK-NEXT:{{^}}global_atomic_add v[3:4], v5, off slc noglc glc
 // CHECK-NEXT:{{^}}                                            ^
 
 s_load_dword s1, s[2:3], 0xfc glc slc
-// CHECK: error: invalid cache policy for SMRD instruction
+// CHECK: error: invalid cache policy for SMEM instruction
 // CHECK-NEXT:{{^}}s_load_dword s1, s[2:3], 0xfc glc slc
 // CHECK-NEXT:{{^}}^

llvm/test/MC/AMDGPU/gfx7_err_pos.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
 //==============================================================================
+// cache policy is not supported for SMRD instructions
+
+s_load_dword s1, s[2:3], 0xfc glc slc
+// CHECK: error: cache policy is not supported for SMRD instructions
+// CHECK-NEXT:{{^}}s_load_dword s1, s[2:3], 0xfc glc slc
+// CHECK-NEXT:{{^}}                              ^
+
+s_load_dword s1, s[2:3], 0xfc slc
+// CHECK: error: cache policy is not supported for SMRD instructions
+// CHECK-NEXT:{{^}}s_load_dword s1, s[2:3], 0xfc slc
+// CHECK-NEXT:{{^}}                              ^
+
+//==============================================================================
 // d16 modifier is not supported on this GPU
 
 image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK: error: d16 modifier is not supported on this GPU
 // CHECK-NEXT:{{^}}image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK-NEXT:{{^}}                                                      ^
 
 //==============================================================================

llvm/test/MC/AMDGPU/smem.s

 // NOGFX1030: error: instruction not supported on this GPU
 
 s_store_dword tma_hi, s[2:3], s4
 // VI: s_store_dword tma_hi, s[2:3], s4 ; encoding: [0xc1,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: register not available on this GPU
 // NOGFX1030: error: instruction not supported on this GPU
 
-// FIXME: Should error on SI instead of silently ignoring glc
 s_load_dword s1, s[2:3], 0xfc glc
 // GFX89: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
 // GFX10: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x01,0xf4,0xfc,0x00,0x00,0xfa]
-// SICI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0xfc,0x83,0x00,0xc0
+// NOSICI: error: cache policy is not supported for SMRD instructions
 
 s_load_dword s1, s[2:3], s4 glc
 // GFX89: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
 // GFX10: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xf4,0x00,0x00,0x00,0x08]
-// SICI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x04,0x82,0x00,0xc0]
+// NOSICI: error: cache policy is not supported for SMRD instructions
 
 s_buffer_store_dword s10, s[92:95], m0
 // GFX89: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // GFX1012: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xf4,0x00,0x00,0x00,0xf8]
 
 s_buffer_store_dword tba_lo, s[92:95], m0
 // VI: s_buffer_store_dword tba_lo, s[92:95], m0 ; encoding: [0x2e,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]

 // NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0
 // VI:    s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1c,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // GFX9:  s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // SICI:  s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x7c,0x5c,0x78,0xc2]
 // GFX10: s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xf4,0x00,0x00,0x00,0xf8]
 
-// FIXME: Should error on SI instead of silently ignoring glc
 s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
 // GFX89: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
 // GFX10: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xf4,0x00,0x00,0x00,0xf8]
-// SICI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x7c,0x5c,0x84,0xc2]
+// NOSICI: error: cache policy is not supported for SMRD instructions
 
 //===----------------------------------------------------------------------===//
 // s_scratch instructions
 //===----------------------------------------------------------------------===//
 
 s_scratch_load_dword s5, s[2:3], s101
 // GFX9: s_scratch_load_dword s5, s[2:3], s101 ; encoding: [0x41,0x01,0x14,0xc0,0x65,0x00,0x00,0x00]
 // GFX1012: s_scratch_load_dword s5, s[2:3], s101 ; encoding: [0x41,0x01,0x14,0xf4,0x00,0x00,0x00,0xca]