[AMDGPU] Remove isLiteralConstant and isLiteralConstantLike

[foad]

Summary

isLiteralConstant and isLiteralConstantLike were similar to
!isInlineConstant with slight differences like handling isReg operands.

To avoid a profusion of similar functions with undocumented differences,
this patch removes all the isLiteralConstant* variants. Callers are responsible
for handling the isReg case.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

3640–3641

This doesn't make any sense to me

[foad]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

3640–3641

Yeah, so this function needs a better name - something that means "is this operand guaranteed not to make the instruction 4 bytes bigger?". I suppose that is (the converse of) what the isLiteralConstantLike name was supposed to imply.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

3640–3641

Most of the uses are checking register as is, so could this just assert on registers?

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

3640–3641

I think this should be an assert and users should have to explicitly look for registers

[foad]

Stop handling register operands in isInlineConstant.

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

for (int OpNo = 0, End = I.getNumOperands(); OpNo < End; ++OpNo) {
             return true;
           continue;
         }
         if (TRI.isSGPRReg(MRI, OpReg))
           return true;
       } else {
         const MCInstrDesc &InstDesc = I.getDesc();
         const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
-        if (TII.isLiteralConstant(Op, OpInfo))
+        if (!TII.isInlineConstant(Op, OpInfo))
           return true;
       }
     }
     return false;
   };
 
   // Check for hazard
   if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) ==

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
 
   // Check the case where we might introduce a second constant operand to a
   // scalar instruction
   if (TII->isSALU(MI->getOpcode())) {
     const MCInstrDesc &InstDesc = MI->getDesc();
     const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
 
     // Fine if the operand can be encoded as an inline constant
-    if (TII->isLiteralConstantLike(*OpToFold, OpInfo)) {
-      if (!TRI->opCanUseInlineConstant(OpInfo.OperandType) ||
-          !TII->isInlineConstant(*OpToFold, OpInfo)) {
-        // Otherwise check for another constant
-        for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) {
-          auto &Op = MI->getOperand(i);
-          if (OpNo != i &&
-              TII->isLiteralConstantLike(Op, OpInfo)) {
-            return false;
-          }
-        }
-      }
-    }
-  }
+    if (!OpToFold->isReg() && !TII->isInlineConstant(*OpToFold, OpInfo)) {
+        if (OpNo != i && !Op.isReg() && !TII->isInlineConstant(Op, OpInfo))
 
   appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
   return true;
 }
 
 // If the use operand doesn't care about the value, this may be an operand only
 // used for register indexing, in which case it is unsafe to fold.
 bool SIFoldOperands::isUseSafeToFold(const MachineInstr &MI,

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
 
   bool isInlineConstant(const APInt &Imm) const;
 
   bool isInlineConstant(const APFloat &Imm) const {
     return isInlineConstant(Imm.bitcastToAPInt());
   }
 
+  // Returns true if this non-register operand definitely does not need to be
+  // encoded as a 32-bit literal. Note that this function handles all kinds of
+  // operands, not just immediates.
+  //
+  // Some operands like FrameIndexes could resolve to an inline immediate value
+  // that will not require an additional 4-bytes; this function assumes that it
+  // will.
   bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
 
   bool isInlineConstant(const MachineOperand &MO,
                         const MCOperandInfo &OpInfo) const {
     return isInlineConstant(MO, OpInfo.OperandType);
   }
 
   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
   }
 
   bool isInlineConstant(const MachineOperand &MO) const {
     const MachineInstr *Parent = MO.getParent();
     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
   }
 
-  bool isLiteralConstant(const MachineOperand &MO,
-                         const MCOperandInfo &OpInfo) const {
-    return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
-  }
-
-  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
-    const MachineOperand &MO = MI.getOperand(OpIdx);
-    return MO.isImm() && !isInlineConstant(MI, OpIdx);
-  }
-
-  // Returns true if this operand could potentially require a 32-bit literal
-  // operand, but not necessarily. A FrameIndex for example could resolve to an
-  // inline immediate value that will not require an additional 4-bytes; this
-  // assumes that it will.
-  bool isLiteralConstantLike(const MachineOperand &MO,
-                             const MCOperandInfo &OpInfo) const;
-
   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
                          const MachineOperand &MO) const;
 
   /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
   /// This function will return false if you pass it a 32-bit instruction.
   bool hasVALU32BitEncoding(unsigned Opcode) const;
 
   /// Returns true if this operand uses the constant bus.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

case AMDGPU::V_MOV_B64_PSEUDO: {
     Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
     Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
 
     const MachineOperand &SrcOp = MI.getOperand(1);
     // FIXME: Will this work for 64-bit floating point immediates?
     assert(!SrcOp.isFPImm());
     if (ST.hasMovB64()) {
       MI.setDesc(get(AMDGPU::V_MOV_B64_e32));
-      if (!isLiteralConstant(MI, 1) || isUInt<32>(SrcOp.getImm()))
+      if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
+          isUInt<32>(SrcOp.getImm()))
         break;
     }
     if (SrcOp.isImm()) {
       APInt Imm(64, SrcOp.getImm());
       APInt Lo(32, Imm.getLoBits(32).getZExtValue());
       APInt Hi(32, Imm.getHiBits(32).getZExtValue());
       if (ST.hasPackedFP32Ops() && Lo == Hi && isInlineConstant(Lo)) {
         BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
return ST.has16BitInsts() &&
                                         ST.hasInv2PiInlineImm());
   default:
     llvm_unreachable("invalid bitwidth");
   }
 }
 
 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
                                    uint8_t OperandType) const {
+  assert(!MO.isReg() && "isInlineConstant called on register operand!");
   if (!MO.isImm() ||
       OperandType < AMDGPU::OPERAND_SRC_FIRST ||
       OperandType > AMDGPU::OPERAND_SRC_LAST)
     return false;
 
   // MachineOperand provides no way to tell the true operand size, since it only
   // records a 64-bit value. We need to know the size to determine if a 32-bit
   // floating point immediate bit pattern is legal for an integer immediate. It
   // would be for any 32-bit integer operand, but would not be for a 64-bit one.
bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
   case AMDGPU::OPERAND_KIMM32:
   case AMDGPU::OPERAND_KIMM16:
     return false;
   default:
     llvm_unreachable("invalid bitwidth");
   }
 }
 
-bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,
-                                        const MCOperandInfo &OpInfo) const {
-  switch (MO.getType()) {
-  case MachineOperand::MO_Register:
-    return false;
-  case MachineOperand::MO_Immediate:
-    return !isInlineConstant(MO, OpInfo);
-  case MachineOperand::MO_FrameIndex:
-  case MachineOperand::MO_MachineBasicBlock:
-  case MachineOperand::MO_ExternalSymbol:
-  case MachineOperand::MO_GlobalAddress:
-  case MachineOperand::MO_MCSymbol:
-    return true;
-  default:
-    llvm_unreachable("unexpected operand type");
-  }
-}
-
 static bool compareMachineOp(const MachineOperand &Op0,
                              const MachineOperand &Op1) {
   if (Op0.getType() != Op1.getType())
     return false;
 
   switch (Op0.getType()) {
   case MachineOperand::MO_Register:
     return Op0.getReg() == Op1.getReg();
MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
 
   return Inst32;
 }
 
 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
                                   const MachineOperand &MO,
                                   const MCOperandInfo &OpInfo) const {
   // Literal constants use the constant bus.
-  //if (isLiteralConstantLike(MO, OpInfo))
-  // return true;
-  if (MO.isImm())
-    return !isInlineConstant(MO, OpInfo);
-
   if (!MO.isReg())
-    return true; // Misc other operands like FrameIndex
+    return !isInlineConstant(MO, OpInfo);
 
   if (!MO.isUse())
     return false;
 
   if (MO.getReg().isVirtual())
     return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
 
   // Null is free
if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32_e64 ||
     }
   }
 
   if (isSOP2(MI) || isSOPC(MI)) {
     const MachineOperand &Src0 = MI.getOperand(Src0Idx);
     const MachineOperand &Src1 = MI.getOperand(Src1Idx);
 
     if (!Src0.isReg() && !Src1.isReg() &&
-        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType) &&
-        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType) &&
+        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx]) &&
+        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx]) &&
         !Src0.isIdenticalTo(Src1)) {
       ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
       return false;
     }
   }
 
   if (isSOPK(MI)) {
     auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
   const TargetRegisterClass *DefinedRC =
       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
   if (!MO)
     MO = &MI.getOperand(OpIdx);
 
   int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode());
   int LiteralLimit = !isVOP3(MI) || ST.hasVOP3Literal() ? 1 : 0;
   if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
-    if (isLiteralConstantLike(*MO, OpInfo) && !LiteralLimit--)
+    if (!MO->isReg() && !isInlineConstant(*MO, OpInfo) && !LiteralLimit--)
       return false;
 
     SmallDenseSet<RegSubRegPair> SGPRsUsed;
     if (MO->isReg())
       SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg()));
 
     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       if (i == OpIdx)
         continue;
       const MachineOperand &Op = MI.getOperand(i);
       if (Op.isReg()) {
         RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
         if (!SGPRsUsed.count(SGPR) &&
             usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
           if (--ConstantBusLimit <= 0)
             return false;
           SGPRsUsed.insert(SGPR);
         }
       } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 ||
                  (AMDGPU::isSISrcOperand(InstDesc, i) &&
-                  isLiteralConstantLike(Op, InstDesc.OpInfo[i]))) {
+                  !isInlineConstant(Op, InstDesc.OpInfo[i]))) {
         if (!LiteralLimit--)
           return false;
         if (--ConstantBusLimit <= 0)
           return false;
       }
     }
   }
 
void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
   MachineOperand &Src0 = MI.getOperand(Src0Idx);
 
   int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
   MachineOperand &Src1 = MI.getOperand(Src1Idx);
 
   // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
   // we need to only have one constant bus use before GFX10.
   bool HasImplicitSGPR = findImplicitSGPRRead(MI);
-  if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 &&
-      Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
-       isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
+  if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 && Src0.isReg() &&
+      RI.isSGPRReg(MRI, Src0.getReg()))
     legalizeOpWithMove(MI, Src0Idx);
 
   // Special case: V_WRITELANE_B32 accepts only immediate or SGPR operands for
   // both the value to write (src0) and lane select (src1).  Fix up non-SGPR
   // src0/src1 with V_READFIRSTLANE.
   if (Opc == AMDGPU::V_WRITELANE_B32) {
     const DebugLoc &DL = MI.getDebugLoc();
     if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
   }
 
   for (int Idx : VOP3Idx) {
     if (Idx == -1)
       break;
     MachineOperand &MO = MI.getOperand(Idx);
 
     if (!MO.isReg()) {
-      if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx]))
+      if (isInlineConstant(MO, get(Opc).OpInfo[Idx]))
         continue;
 
       if (LiteralLimit > 0 && ConstantBusLimit > 0) {
         --LiteralLimit;
         --ConstantBusLimit;
         continue;
       }
 
unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   // operands that could ever be literals.
   if (isVALU(MI) || isSALU(MI)) {
     if (isDPP(MI))
       return DescSize;
     bool HasLiteral = false;
     for (int I = 0, E = MI.getNumExplicitOperands(); I != E; ++I) {
       const MachineOperand &Op = MI.getOperand(I);
       const MCOperandInfo &OpInfo = Desc.OpInfo[I];
-      if (isLiteralConstantLike(Op, OpInfo)) {
+      if (!Op.isReg() && !isInlineConstant(Op, OpInfo)) {
         HasLiteral = true;
         break;
       }
     }
     return HasLiteral ? DescSize + 4 : DescSize;
   }
 
   // Check whether we have extra NSA words.