[PowerPC][AIX] Allow VSX patterns to be 32-bit and 64-bit safe on P8+.

[amyk]

Summary

This patch updates two patterns involving scalar_to_vector and
SCALAR_TO_VECTOR_PERMUTED nodes to be safe for both 64-bit and 32-bit by
pulling the patterns out of the 64-bit specific guard.

These patterns are matched on POWER8 and above.

[amyk]

Ping.

[lei]

LGTM
Thx for fixing this.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
 
 def : Pat<(f32 (vector_extract v4f32:$S, i32:$Idx)),
           (f32 VectorExtractions.BE_32B_VARIABLE_FLOAT)>;
 
 def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)),
           (f64 VectorExtractions.BE_32B_VARIABLE_DOUBLE)>;
+
+defm : ScalToVecWPermute<
+  v4i32, (i32 (load ForceXForm:$src)),
+  (XXSLDWIs (LIWZX ForceXForm:$src), 1),
+  (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
+defm : ScalToVecWPermute<
+  v4f32, (f32 (load ForceXForm:$src)),
+  (XXSLDWIs (LIWZX ForceXForm:$src), 1),
+  (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 } // HasVSX, HasP8Vector, IsBigEndian
 
 // Big endian Power8 64Bit VSX subtarget.
 let Predicates = [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] in {
 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
           (f32 VectorExtractions.BE_VARIABLE_FLOAT)>;
 
 // LIWAX - This instruction is used for sign extending i32 -> i64.
 // LIWZX - This instruction will be emitted for i32, f32, and when
 //         zero-extending i32 to i64 (zext i32 -> i64).
 def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))),
           (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>;
 def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))),
           (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>;
-defm : ScalToVecWPermute<
-  v4i32, (i32 (load ForceXForm:$src)),
-  (XXSLDWIs (LIWZX ForceXForm:$src), 1),
-  (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
-defm : ScalToVecWPermute<
-  v4f32, (f32 (load ForceXForm:$src)),
-  (XXSLDWIs (LIWZX ForceXForm:$src), 1),
-  (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 def : Pat<DWToSPExtractConv.BVU,
           (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3),
                           (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>;
 def : Pat<DWToSPExtractConv.BVS,
           (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3),
                           (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>;
 def : Pat<(store (i32 (extractelt v4i32:$A, 1)), ForceXForm:$src),

llvm/test/CodeGen/PowerPC/aix_scalar_vector_permuted.ll

 ; AIX-P8-64-NEXT:    lfdx f0, 0, r3
 ; AIX-P8-64-NEXT:    lfdx f1, 0, r4
 ; AIX-P8-64-NEXT:    xvaddsp vs0, vs0, vs1
 ; AIX-P8-64-NEXT:    stfdx f0, 0, r5
 ; AIX-P8-64-NEXT:    blr
 ;
 ; AIX-P8-32-LABEL: test_f2:
 ; AIX-P8-32:       # %bb.0:
-; AIX-P8-32-NEXT:    lfs f0, 4(r3)
-; AIX-P8-32-NEXT:    lfs f1, 0(r3)
 ; AIX-P8-32-NEXT:    lwz r6, L..C0(r2) # %const.0
-; AIX-P8-32-NEXT:    lfs f2, 4(r4)
-; AIX-P8-32-NEXT:    xscvdpspn v2, f0
-; AIX-P8-32-NEXT:    lfs f0, 0(r4)
-; AIX-P8-32-NEXT:    lxvw4x v0, 0, r6
-; AIX-P8-32-NEXT:    xscvdpspn v3, f1
-; AIX-P8-32-NEXT:    xscvdpspn v4, f2
-; AIX-P8-32-NEXT:    xscvdpspn v5, f0
-; AIX-P8-32-NEXT:    vperm v2, v3, v2, v0
-; AIX-P8-32-NEXT:    vperm v3, v5, v4, v0
+; AIX-P8-32-NEXT:    li r7, 4
+; AIX-P8-32-NEXT:    lxsiwzx v3, 0, r3
+; AIX-P8-32-NEXT:    lxsiwzx v0, 0, r4
+; AIX-P8-32-NEXT:    lxsiwzx v2, r3, r7
+; AIX-P8-32-NEXT:    lxsiwzx v5, r4, r7
+; AIX-P8-32-NEXT:    lxvw4x v4, 0, r6
+; AIX-P8-32-NEXT:    vperm v2, v3, v2, v4
+; AIX-P8-32-NEXT:    vperm v3, v0, v5, v4
 ; AIX-P8-32-NEXT:    xvaddsp vs0, v2, v3
 ; AIX-P8-32-NEXT:    xxsldwi vs1, vs0, vs0, 1
 ; AIX-P8-32-NEXT:    xscvspdpn f0, vs0
 ; AIX-P8-32-NEXT:    xscvspdpn f1, vs1
 ; AIX-P8-32-NEXT:    stfs f0, 0(r5)
 ; AIX-P8-32-NEXT:    stfs f1, 4(r5)
 ; AIX-P8-32-NEXT:    blr
 ;
 ; AIX-P9-64-LABEL: test_f2:
 ; AIX-P9-64:       # %bb.0:
 ; AIX-P9-64-NEXT:    lfd f0, 0(r3)
 ; AIX-P9-64-NEXT:    lfd f1, 0(r4)
 ; AIX-P9-64-NEXT:    xvaddsp vs0, vs0, vs1
 ; AIX-P9-64-NEXT:    stfd f0, 0(r5)
 ; AIX-P9-64-NEXT:    blr
 ;
 ; AIX-P9-32-LABEL: test_f2:
 ; AIX-P9-32:       # %bb.0:
-; AIX-P9-32-NEXT:    lfs f0, 0(r3)
+; AIX-P9-32-NEXT:    lfiwzx f0, 0, r3
 ; AIX-P9-32-NEXT:    lwz r3, 4(r3)
+; AIX-P9-32-NEXT:    xxsldwi vs0, f0, f0, 1
 ; AIX-P9-32-NEXT:    mtfprwz f1, r3
 ; AIX-P9-32-NEXT:    lwz r3, 4(r4)
-; AIX-P9-32-NEXT:    xscvdpspn vs0, f0
-; AIX-P9-32-NEXT:    mtfprwz f2, r3
 ; AIX-P9-32-NEXT:    xxinsertw vs0, vs1, 4
-; AIX-P9-32-NEXT:    lfs f1, 0(r4)
-; AIX-P9-32-NEXT:    xscvdpspn vs1, f1
+; AIX-P9-32-NEXT:    lfiwzx f1, 0, r4
+; AIX-P9-32-NEXT:    mtfprwz f2, r3
+; AIX-P9-32-NEXT:    xxsldwi vs1, f1, f1, 1
 ; AIX-P9-32-NEXT:    xxinsertw vs1, vs2, 4
 ; AIX-P9-32-NEXT:    xvaddsp vs0, vs0, vs1
 ; AIX-P9-32-NEXT:    xscvspdpn f1, vs0
 ; AIX-P9-32-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; AIX-P9-32-NEXT:    xscvspdpn f0, vs0
 ; AIX-P9-32-NEXT:    stfs f1, 0(r5)
 ; AIX-P9-32-NEXT:    stfs f0, 4(r5)
 ; AIX-P9-32-NEXT:    blr
   %p = load %f2, %f2* %P
   %q = load %f2, %f2* %Q
   %R = fadd %f2 %p, %q
   store %f2 %R, %f2* %S
   ret void
 }
 

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; P8-AIX-64-LABEL: testSplat4hi:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    lfdx f0, 0, r3
 ; P8-AIX-64-NEXT:    xxspltw v2, vs0, 0
 ; P8-AIX-64-NEXT:    blr
 ;
 ; P8-AIX-32-LABEL: testSplat4hi:
 ; P8-AIX-32:       # %bb.0: # %entry
-; P8-AIX-32-NEXT:    lwz r3, 0(r3)
-; P8-AIX-32-NEXT:    mtfprwz f0, r3
+; P8-AIX-32-NEXT:    lfiwzx f0, 0, r3
 ; P8-AIX-32-NEXT:    xxspltw v2, vs0, 1
 ; P8-AIX-32-NEXT:    blr
 entry:
   %0 = load <8 x i8>, <8 x i8>* %ptr, align 8
   %vecinit22 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %1 = bitcast <16 x i8> %vecinit22 to <4 x i32>
   ret <4 x i32> %1
 }

llvm/test/CodeGen/PowerPC/float-vector-gather.ll

 ; CHECK-BE-DAG:    lfiwzx f[[REG3:[0-9]+]], 0, r6
 ; CHECK-BE-DAG:    xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]
 ; CHECK-BE-DAG:    xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]
 ; CHECK-BE-NEXT:   xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]
 ; CHECK-BE-NEXT:   blr
 
 ; CHECK-BE-AIX-32-LABEL: vector_gatherf:
 ; CHECK-BE-AIX-32-LABEL: # %bb.0: # %entry
-; CHECK-BE-AIX-32-DAG: lfs f[[REG0:[0-9]+]]
-; CHECK-BE-AIX-32-DAG: lfs f[[REG1:[0-9]+]]
-; CHECK-BE-AIX-32-DAG: lfs f[[REG2:[0-9]+]]
-; CHECK-BE-AIX-32-DAG: lfs f[[REG3:[0-9]+]]
-; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG0:[0-9]+]], f[[REG0]]
-; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG1:[0-9]+]], f[[REG1]]
-; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG2:[0-9]+]], f[[REG2]]
-; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG0:[0-9]+]], f[[REG3]]
-; CHECK-BE-AIX-32-DAG: vmrgow v[[VREG1]], v[[VREG0]], v[[VREG1]]
-; CHECK-BE-AIX-32-DAG: vmrgow v[[VREG0]], v[[VREG2]], v[[VREG0]]
-; CHECK-BE-AIX-32-NEXT: xxmrghd v[[VREG1]], v[[VREG0]], v[[VREG1]]
+; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG0:[0-9]+]]
+; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG1:[0-9]+]]
+; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG2:[0-9]+]]
+; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG3:[0-9]+]]
+; CHECK-BE-AIX-32-DAG: vmrgow v[[REG0]], v[[REG1]], v[[REG0]]
+; CHECK-BE-AIX-32-DAG: vmrgow v[[REG3]], v[[REG2]], v[[REG3]]
+; CHECK-BE-AIX-32-NEXT: xxmrghd v[[REG0]], v[[REG3]], v[[REG0]]
 ; CHECK-BE-AIX-32-NEXT: blr
 entry:
   %0 = load float, float* %a, align 4
   %vecinit = insertelement <4 x float> undef, float %0, i32 0
   %1 = load float, float* %b, align 4
   %vecinit1 = insertelement <4 x float> %vecinit, float %1, i32 1
   %2 = load float, float* %c, align 4
   %vecinit2 = insertelement <4 x float> %vecinit1, float %2, i32 2
   %3 = load float, float* %d, align 4
   %vecinit3 = insertelement <4 x float> %vecinit2, float %3, i32 3
   ret <4 x float> %vecinit3
 }
 

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ;
 ; P9-AIX32-LABEL: unadjusted_lxvwsx:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: unadjusted_lxvwsx:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lwz r3, 0(r3)
-; P8-AIX32-NEXT:    mtfprwz f0, r3
+; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
 ; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: unadjusted_lxvwsx:
 ; P7-AIX32:       # %bb.0: # %entry
 ; P7-AIX32-NEXT:    lwz r3, 0(r3)
 ; P7-AIX32-NEXT:    addi r4, r1, -16
 ; P7-AIX32-NEXT:    stw r3, -16(r1)

llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll

 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-32-LABEL: test:
 ; CHECK-AIX-32:       # %bb.0: # %entry
-; CHECK-AIX-32-NEXT:    lwz r3, 0(r3)
-; CHECK-AIX-32-NEXT:    mtfprwz f0, r3
+; CHECK-AIX-32-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-AIX-32-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-AIX-32-NEXT:    blr
 
 entry:
   %0 = bitcast i32* %s to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 4
   %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   ret <16 x i8> %2
 }

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; CHECK: lxsiwzx [[REG:[0-9]+]]
 ; CHECK: vperm {{[0-9]+}}, [[REG]]
 ; P9BE-LABEL: test32:
 ; P9BE-NOT: lwzux
 ; P9BE-NOT: mtvsrwz
 ; P9BE: lxsiwzx [[REG:[0-9]+]]
 ; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
 ; P9BE-32-LABEL: test32:
-; P9BE-32: lwzx [[REG1:[0-9]+]]
-; P9BE-32: mtvsrwz [[REG2:[0-9]+]], [[REG1]]
-; P9BE-32: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
+; P9BE-32: lxsiwzx [[REG:[0-9]+]]
+; P9BE-32: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
 entry:
   %idx.ext63 = sext i32 %i_pix2 to i64
   %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
   %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
   %0 = bitcast i8* %add.ptr64 to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   %2 = zext <4 x i8> %reorder_shuffle117 to <4 x i32>

llvm/test/CodeGen/PowerPC/reduce_scalarization.ll

 ; AIX-64-NEXT:    lfdx f1, 0, r4
 ; AIX-64-NEXT:    xvsubsp vs0, vs0, vs1
 ; AIX-64-NEXT:    xxmrghw vs0, vs0, vs0
 ; AIX-64-NEXT:    xvcvspdp v2, vs0
 ; AIX-64-NEXT:    blr
 ;
 ; AIX-32-LABEL: test2:
 ; AIX-32:       # %bb.0: # %entry
-; AIX-32-NEXT:    lfs f0, 4(r3)
-; AIX-32-NEXT:    lfs f1, 0(r3)
 ; AIX-32-NEXT:    lwz r5, L..C0(r2) # %const.0
-; AIX-32-NEXT:    lfs f2, 4(r4)
-; AIX-32-NEXT:    xscvdpspn v2, f0
-; AIX-32-NEXT:    lfs f0, 0(r4)
-; AIX-32-NEXT:    lxvw4x v0, 0, r5
-; AIX-32-NEXT:    xscvdpspn v3, f1
-; AIX-32-NEXT:    xscvdpspn v4, f2
-; AIX-32-NEXT:    xscvdpspn v5, f0
-; AIX-32-NEXT:    vperm v2, v3, v2, v0
-; AIX-32-NEXT:    vperm v3, v5, v4, v0
+; AIX-32-NEXT:    li r6, 4
+; AIX-32-NEXT:    lxsiwzx v3, 0, r3
+; AIX-32-NEXT:    lxsiwzx v0, 0, r4
+; AIX-32-NEXT:    lxsiwzx v2, r3, r6
+; AIX-32-NEXT:    lxsiwzx v5, r4, r6
+; AIX-32-NEXT:    lxvw4x v4, 0, r5
+; AIX-32-NEXT:    vperm v2, v3, v2, v4
+; AIX-32-NEXT:    vperm v3, v0, v5, v4
 ; AIX-32-NEXT:    xvsubsp vs0, v2, v3
 ; AIX-32-NEXT:    xxsldwi vs1, vs0, vs0, 1
 ; AIX-32-NEXT:    xscvspdpn f0, vs0
 ; AIX-32-NEXT:    xscvspdpn f1, vs1
 ; AIX-32-NEXT:    xxmrghd v2, vs0, vs1
 ; AIX-32-NEXT:    blr
 entry:
   %0 = load <2 x float>, <2 x float>* %a, align 8

 ; AIX-64-NEXT:    lfdx f1, 0, r4
 ; AIX-64-NEXT:    xvaddsp vs0, vs0, vs1
 ; AIX-64-NEXT:    xxmrghw vs0, vs0, vs0
 ; AIX-64-NEXT:    xvcvspdp v2, vs0
 ; AIX-64-NEXT:    blr
 ;
 ; AIX-32-LABEL: test3:
 ; AIX-32:       # %bb.0: # %entry
-; AIX-32-NEXT:    lfs f0, 4(r3)
-; AIX-32-NEXT:    lfs f1, 0(r3)
 ; AIX-32-NEXT:    lwz r5, L..C1(r2) # %const.0
-; AIX-32-NEXT:    lfs f2, 4(r4)
-; AIX-32-NEXT:    xscvdpspn v2, f0
-; AIX-32-NEXT:    lfs f0, 0(r4)
-; AIX-32-NEXT:    lxvw4x v0, 0, r5
-; AIX-32-NEXT:    xscvdpspn v3, f1
-; AIX-32-NEXT:    xscvdpspn v4, f2
-; AIX-32-NEXT:    xscvdpspn v5, f0
-; AIX-32-NEXT:    vperm v2, v3, v2, v0
-; AIX-32-NEXT:    vperm v3, v5, v4, v0
+; AIX-32-NEXT:    li r6, 4
+; AIX-32-NEXT:    lxsiwzx v3, 0, r3
+; AIX-32-NEXT:    lxsiwzx v0, 0, r4
+; AIX-32-NEXT:    lxsiwzx v2, r3, r6
+; AIX-32-NEXT:    lxsiwzx v5, r4, r6
+; AIX-32-NEXT:    lxvw4x v4, 0, r5
+; AIX-32-NEXT:    vperm v2, v3, v2, v4
+; AIX-32-NEXT:    vperm v3, v0, v5, v4
 ; AIX-32-NEXT:    xvaddsp vs0, v2, v3
 ; AIX-32-NEXT:    xxsldwi vs1, vs0, vs0, 1
 ; AIX-32-NEXT:    xscvspdpn f0, vs0
 ; AIX-32-NEXT:    xscvspdpn f1, vs1
 ; AIX-32-NEXT:    xxmrghd v2, vs0, vs1
 ; AIX-32-NEXT:    blr
 entry:
   %0 = load <2 x float>, <2 x float>* %a, align 8

 ; AIX-64-NEXT:    lfdx f1, 0, r4
 ; AIX-64-NEXT:    xvmulsp vs0, vs0, vs1
 ; AIX-64-NEXT:    xxmrghw vs0, vs0, vs0
 ; AIX-64-NEXT:    xvcvspdp v2, vs0
 ; AIX-64-NEXT:    blr
 ;
 ; AIX-32-LABEL: test4:
 ; AIX-32:       # %bb.0: # %entry
-; AIX-32-NEXT:    lfs f0, 4(r3)
-; AIX-32-NEXT:    lfs f1, 0(r3)
 ; AIX-32-NEXT:    lwz r5, L..C2(r2) # %const.0
-; AIX-32-NEXT:    lfs f2, 4(r4)
-; AIX-32-NEXT:    xscvdpspn v2, f0
-; AIX-32-NEXT:    lfs f0, 0(r4)
-; AIX-32-NEXT:    lxvw4x v0, 0, r5
-; AIX-32-NEXT:    xscvdpspn v3, f1
-; AIX-32-NEXT:    xscvdpspn v4, f2
-; AIX-32-NEXT:    xscvdpspn v5, f0
-; AIX-32-NEXT:    vperm v2, v3, v2, v0
-; AIX-32-NEXT:    vperm v3, v5, v4, v0
+; AIX-32-NEXT:    li r6, 4
+; AIX-32-NEXT:    lxsiwzx v3, 0, r3
+; AIX-32-NEXT:    lxsiwzx v0, 0, r4
+; AIX-32-NEXT:    lxsiwzx v2, r3, r6
+; AIX-32-NEXT:    lxsiwzx v5, r4, r6
+; AIX-32-NEXT:    lxvw4x v4, 0, r5
+; AIX-32-NEXT:    vperm v2, v3, v2, v4
+; AIX-32-NEXT:    vperm v3, v0, v5, v4
 ; AIX-32-NEXT:    xvmulsp vs0, v2, v3
 ; AIX-32-NEXT:    xxsldwi vs1, vs0, vs0, 1
 ; AIX-32-NEXT:    xscvspdpn f0, vs0
 ; AIX-32-NEXT:    xscvspdpn f1, vs1
 ; AIX-32-NEXT:    xxmrghd v2, vs0, vs1
 ; AIX-32-NEXT:    blr
 entry:
   %0 = load <2 x float>, <2 x float>* %a, align 8

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
 
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-ibm-aix-xcoff< %s | FileCheck %s \
-; RUN:    --check-prefixes=P9-AIX,P9-AIX-64
+; RUN:    --check-prefixes=AIX,P9-AIX,P9-AIX-64
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
-; RUN:    --check-prefixes=P9-AIX,P9-AIX-32
+; RUN:    --check-prefixes=AIX,P9-AIX,P9-AIX-32
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
-; RUN:    --check-prefixes=P8-AIX-64
+; RUN:    --check-prefixes=AIX,P8-AIX-64
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
-; RUN:    --check-prefixes=P8-AIX-32
+; RUN:    --check-prefixes=AIX,P8-AIX-32
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x i32> @s2v_test1(i32* nocapture readonly %int32, <4 x i32> %vec)  {
 ; P9LE-LABEL: s2v_test1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lwz r3, 0(r3)
 ; P9LE-NEXT:    mtfprwz f0, r3
 ; P9LE-NEXT:    xxinsertw v2, vs0, 12

 ; P8-AIX-64-NEXT:    ld r4, L..C5(r2) # %const.0
 ; P8-AIX-64-NEXT:    lxsiwzx v3, 0, r3
 ; P8-AIX-64-NEXT:    lxvw4x v4, 0, r4
 ; P8-AIX-64-NEXT:    vperm v2, v3, v2, v4
 ; P8-AIX-64-NEXT:    blr
 ;
 ; P8-AIX-32-LABEL: s2v_test_f1:
 ; P8-AIX-32:       # %bb.0: # %entry
-; P8-AIX-32-NEXT:    lfs f0, 0(r3)
 ; P8-AIX-32-NEXT:    lwz r4, L..C5(r2) # %const.0
-; P8-AIX-32-NEXT:    xscvdpspn v3, f0
+; P8-AIX-32-NEXT:    lxsiwzx v3, 0, r3
 ; P8-AIX-32-NEXT:    lxvw4x v4, 0, r4
 ; P8-AIX-32-NEXT:    vperm v2, v3, v2, v4
 ; P8-AIX-32-NEXT:    blr
 entry:
   %0 = load float, float* %f64, align 4
   %vecins = insertelement <4 x float> %vec, float %0, i32 0
   ret <4 x float> %vecins
 }

 ;
 ; P8BE-LABEL: s2v_test_f2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
 ; P8BE-NEXT:    lxsiwzx v3, 0, r3
 ; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 ;
-; P9-AIX-64-LABEL: s2v_test_f2:
-; P9-AIX-64:       # %bb.0: # %entry
-; P9-AIX-64-NEXT:    addi r3, r3, 4
-; P9-AIX-64-NEXT:    lxsiwzx v3, 0, r3
-; P9-AIX-64-NEXT:    vmrgow v2, v3, v2
-; P9-AIX-64-NEXT:    blr
-;
-; P9-AIX-32-LABEL: s2v_test_f2:
-; P9-AIX-32:       # %bb.0: # %entry
-; P9-AIX-32-NEXT:    lfs f0, 4(r3)
-; P9-AIX-32-NEXT:    xscvdpspn v3, f0
-; P9-AIX-32-NEXT:    vmrgow v2, v3, v2
-; P9-AIX-32-NEXT:    blr
-;
-; P8-AIX-64-LABEL: s2v_test_f2:
-; P8-AIX-64:       # %bb.0: # %entry
-; P8-AIX-64-NEXT:    addi r3, r3, 4
-; P8-AIX-64-NEXT:    lxsiwzx v3, 0, r3
-; P8-AIX-64-NEXT:    vmrgow v2, v3, v2
-; P8-AIX-64-NEXT:    blr
-;
-; P8-AIX-32-LABEL: s2v_test_f2:
-; P8-AIX-32:       # %bb.0: # %entry
-; P8-AIX-32-NEXT:    lfs f0, 4(r3)
-; P8-AIX-32-NEXT:    xscvdpspn v3, f0
-; P8-AIX-32-NEXT:    vmrgow v2, v3, v2
-; P8-AIX-32-NEXT:    blr
+; AIX-LABEL: s2v_test_f2:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    addi r3, r3, 4
+; AIX-NEXT:    lxsiwzx v3, 0, r3
+; AIX-NEXT:    vmrgow v2, v3, v2
+; AIX-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %f64, i64 1
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly

 ; P9-AIX-64-NEXT:    sldi r4, r4, 2
 ; P9-AIX-64-NEXT:    lxsiwzx v3, r3, r4
 ; P9-AIX-64-NEXT:    vmrgow v2, v3, v2
 ; P9-AIX-64-NEXT:    blr
 ;
 ; P9-AIX-32-LABEL: s2v_test_f3:
 ; P9-AIX-32:       # %bb.0: # %entry
 ; P9-AIX-32-NEXT:    slwi r4, r4, 2
-; P9-AIX-32-NEXT:    lfsx f0, r3, r4
-; P9-AIX-32-NEXT:    xscvdpspn v3, f0
+; P9-AIX-32-NEXT:    lxsiwzx v3, r3, r4
 ; P9-AIX-32-NEXT:    vmrgow v2, v3, v2
 ; P9-AIX-32-NEXT:    blr
 ;
 ; P8-AIX-64-LABEL: s2v_test_f3:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    sldi r4, r4, 2
 ; P8-AIX-64-NEXT:    lxsiwzx v3, r3, r4
 ; P8-AIX-64-NEXT:    vmrgow v2, v3, v2
 ; P8-AIX-64-NEXT:    blr
 ;
 ; P8-AIX-32-LABEL: s2v_test_f3:
 ; P8-AIX-32:       # %bb.0: # %entry
 ; P8-AIX-32-NEXT:    slwi r4, r4, 2
-; P8-AIX-32-NEXT:    lfsx f0, r3, r4
-; P8-AIX-32-NEXT:    xscvdpspn v3, f0
+; P8-AIX-32-NEXT:    lxsiwzx v3, r3, r4
 ; P8-AIX-32-NEXT:    vmrgow v2, v3, v2
 ; P8-AIX-32-NEXT:    blr
 entry:
   %idxprom = sext i32 %Idx to i64
   %arrayidx = getelementptr inbounds float, float* %f64, i64 %idxprom
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins

 ;
 ; P8BE-LABEL: s2v_test_f4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
 ; P8BE-NEXT:    lxsiwzx v3, 0, r3
 ; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 ;
-; P9-AIX-64-LABEL: s2v_test_f4:
-; P9-AIX-64:       # %bb.0: # %entry
-; P9-AIX-64-NEXT:    addi r3, r3, 4
-; P9-AIX-64-NEXT:    lxsiwzx v3, 0, r3
-; P9-AIX-64-NEXT:    vmrgow v2, v3, v2
-; P9-AIX-64-NEXT:    blr
-;
-; P9-AIX-32-LABEL: s2v_test_f4:
-; P9-AIX-32:       # %bb.0: # %entry
-; P9-AIX-32-NEXT:    lfs f0, 4(r3)
-; P9-AIX-32-NEXT:    xscvdpspn v3, f0
-; P9-AIX-32-NEXT:    vmrgow v2, v3, v2
-; P9-AIX-32-NEXT:    blr
-;
-; P8-AIX-64-LABEL: s2v_test_f4:
-; P8-AIX-64:       # %bb.0: # %entry
-; P8-AIX-64-NEXT:    addi r3, r3, 4
-; P8-AIX-64-NEXT:    lxsiwzx v3, 0, r3
-; P8-AIX-64-NEXT:    vmrgow v2, v3, v2
-; P8-AIX-64-NEXT:    blr
-;
-; P8-AIX-32-LABEL: s2v_test_f4:
-; P8-AIX-32:       # %bb.0: # %entry
-; P8-AIX-32-NEXT:    lfs f0, 4(r3)
-; P8-AIX-32-NEXT:    xscvdpspn v3, f0
-; P8-AIX-32-NEXT:    vmrgow v2, v3, v2
-; P8-AIX-32-NEXT:    blr
+; AIX-LABEL: s2v_test_f4:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    addi r3, r3, 4
+; AIX-NEXT:    lxsiwzx v3, 0, r3
+; AIX-NEXT:    vmrgow v2, v3, v2
+; AIX-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %f64, i64 1
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly

 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f5:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lxsiwzx v3, 0, r5
 ; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 ;
-; P9-AIX-64-LABEL: s2v_test_f5:
-; P9-AIX-64:       # %bb.0: # %entry
-; P9-AIX-64-NEXT:    lxsiwzx v3, 0, r3
-; P9-AIX-64-NEXT:    vmrgow v2, v3, v2
-; P9-AIX-64-NEXT:    blr
-;
-; P9-AIX-32-LABEL: s2v_test_f5:
-; P9-AIX-32:       # %bb.0: # %entry
-; P9-AIX-32-NEXT:    lfs f0, 0(r3)
-; P9-AIX-32-NEXT:    xscvdpspn v3, f0
-; P9-AIX-32-NEXT:    vmrgow v2, v3, v2
-; P9-AIX-32-NEXT:    blr
-;
-; P8-AIX-64-LABEL: s2v_test_f5:
-; P8-AIX-64:       # %bb.0: # %entry
-; P8-AIX-64-NEXT:    lxsiwzx v3, 0, r3
-; P8-AIX-64-NEXT:    vmrgow v2, v3, v2
-; P8-AIX-64-NEXT:    blr
-;
-; P8-AIX-32-LABEL: s2v_test_f5:
-; P8-AIX-32:       # %bb.0: # %entry
-; P8-AIX-32-NEXT:    lfs f0, 0(r3)
-; P8-AIX-32-NEXT:    xscvdpspn v3, f0
-; P8-AIX-32-NEXT:    vmrgow v2, v3, v2
-; P8-AIX-32-NEXT:    blr
+; AIX-LABEL: s2v_test_f5:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxsiwzx v3, 0, r3
+; AIX-NEXT:    vmrgow v2, v3, v2
+; AIX-NEXT:    blr
 entry:
   %0 = load float, float* %ptr1, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

 ; AIX-P8-64-NEXT:    vperm v2, v3, v2, v4
 ; AIX-P8-64-NEXT:    lxsiwzx v3, r3, r5
 ; AIX-P8-64-NEXT:    lxvw4x v4, 0, r4
 ; AIX-P8-64-NEXT:    vperm v2, v2, v3, v4
 ; AIX-P8-64-NEXT:    blr
 ;
 ; AIX-P8-32-LABEL: testFloatImm2:
 ; AIX-P8-32:       # %bb.0: # %entry
-; AIX-P8-32-NEXT:    lfs f0, 0(r3)
 ; AIX-P8-32-NEXT:    lwz r4, L..C8(r2) # %const.0
-; AIX-P8-32-NEXT:    xscvdpspn v3, f0
+; AIX-P8-32-NEXT:    lxsiwzx v3, 0, r3
+; AIX-P8-32-NEXT:    li r5, 4
 ; AIX-P8-32-NEXT:    lxvw4x v4, 0, r4
-; AIX-P8-32-NEXT:    lfs f0, 4(r3)
-; AIX-P8-32-NEXT:    lwz r3, L..C9(r2) # %const.1
+; AIX-P8-32-NEXT:    lwz r4, L..C9(r2) # %const.1
 ; AIX-P8-32-NEXT:    vperm v2, v3, v2, v4
-; AIX-P8-32-NEXT:    lxvw4x v4, 0, r3
-; AIX-P8-32-NEXT:    xscvdpspn v3, f0
+; AIX-P8-32-NEXT:    lxsiwzx v3, r3, r5
+; AIX-P8-32-NEXT:    lxvw4x v4, 0, r4
 ; AIX-P8-32-NEXT:    vperm v2, v2, v3, v4
 ; AIX-P8-32-NEXT:    blr
 entry:
   %0 = bitcast i32* %b to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 0

 ; AIX-P8-64-NEXT:    vperm v2, v3, v2, v4
 ; AIX-P8-64-NEXT:    lxsiwzx v3, r3, r5
 ; AIX-P8-64-NEXT:    lxvw4x v4, 0, r4
 ; AIX-P8-64-NEXT:    vperm v2, v2, v3, v4
 ; AIX-P8-64-NEXT:    blr
 ;
 ; AIX-P8-32-LABEL: testFloatImm3:
 ; AIX-P8-32:       # %bb.0: # %entry
-; AIX-P8-32-NEXT:    lis r4, 4
-; AIX-P8-32-NEXT:    lfsx f0, r3, r4
 ; AIX-P8-32-NEXT:    lwz r4, L..C10(r2) # %const.0
-; AIX-P8-32-NEXT:    xscvdpspn v3, f0
+; AIX-P8-32-NEXT:    lis r5, 4
+; AIX-P8-32-NEXT:    lxsiwzx v3, r3, r5
 ; AIX-P8-32-NEXT:    lxvw4x v4, 0, r4
-; AIX-P8-32-NEXT:    lfs f0, 0(r3)
-; AIX-P8-32-NEXT:    lwz r3, L..C11(r2) # %const.1
+; AIX-P8-32-NEXT:    lwz r4, L..C11(r2) # %const.1
 ; AIX-P8-32-NEXT:    vperm v2, v3, v2, v4
-; AIX-P8-32-NEXT:    lxvw4x v4, 0, r3
-; AIX-P8-32-NEXT:    xscvdpspn v3, f0
-; AIX-P8-32-NEXT:    vperm v2, v2, v3, v4
+; AIX-P8-32-NEXT:    lxvw4x v3, 0, r4
+; AIX-P8-32-NEXT:    lxsiwzx v4, 0, r3
+; AIX-P8-32-NEXT:    vperm v2, v2, v4, v3
 ; AIX-P8-32-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
   %0 = bitcast i32* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 0